AU649476B2 - Integrated circuit comprising a standard cell, an application cell and a test cell - Google Patents

Description

o49476 P/00/011 28/5/91 Regulation 3.2

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COMPLETE SPECIFICATION STANDARD PATENT Invention Title: "INTEGRATED CIRCUIT COMVPRISING A. STANDARD CELL, AN APPLICATION CELL, AND A TEST CELL" The following( statcnlt is a full description of this invention, iinCILuding the best method of Performing iL kiuwn~l to uls:- This invention concerns an integrated circuit comprising a standard cell, an application cell and a test cell designed in particular to monitor communication signals between the previous two cells.

Modern electronic devices, and especially those which process digital signals, often comprise a programmable unit such as a microprocessor associated with a program memory and an application circuit combining peripheral circuits of the programmable unit and logic circuits specific to the functions that thse devices implement. They are routinely mounted on an electronic circuit )oard on which the programmable unit and its memory are two standard components whereas the application circuit is usually an application-specific integrated circuit. The connections between these three components are therefore all visible on the circuit board and test or emulation equipment can therefore access them during the various test and debugging phases of the development of such 'device, Technological advances in the field of microelectronics now make it feasible to 15 integrate in a single component the various devices that were previously mounted on A k* a circuit board of this kind. The programmable unit is usually a standard cell defined "00 by the manufacturer whereas the application circuit is specified by the component .e a designer. The program memory is also usually a standard sub-system which in this 11 I l disclosure will be arbitrarily combined with the application circuit to constitute what is referred to hereinafter as the "application cell". With this mode of implementation the only device connections accessible are the component leads which are reduced in number as compared to a printed circuit board implementation because most of the 0 communication links between the standard cell and the application cell are not connected to pins. It is not desirable to increase significantly the number of pins as this 25 increases the size and the cost of the component. It may even be ruled out by virtue of the technology employed. As a result, it is impossible to use known test and emulation methods on such components. The successive stages which previously consisted in debugging the application cell, developing the programming memory software, debugging this software and finally debugging the device as a whole can no longer be dissociated.

It is possible to use a computer-aided design tool to simulate the interaction between the standard cell and the application cell. In this way it is possible to verify mainly the operation of the communication links between the two cells. However, such simulations are time-consuming and costly given the computing power of the 3 simulation tools. Component development and debugging times become incompatible with industrial constraints.

It is also possible to obtain from some manufacturers a component kit in which the programmable unit and the application cell are separate devices. During the test phase, the device is implemented as a mock-up in which the connections between the two components are accessible and so can be treated in a similar way to connections on electronic circuit boards. In this case the mock-up development cost is additional to the cost of the fully integrated component. Also, the performance of the mock-up device, and in particular its execution speed, are significantly degraded in comparison with what can be expected of the same device in its integrated version. It is therefore impossible to reproduce this version in all respects. The problem of limited speed is particularly accentuated if the programmable unit is a signal processor. The "boundary scan" t-st and emulation technique described in particular in IEEE (Institute of Electrical and Electronic Engineers) standard 1149.1 is used in the case of o, 15 a fully integrated component. In this technique, a test cell is disposed between the standard cell and the application cell. It comprises, for each communication link, a *q scanning unit provided with a unit memory, these unit memories being interconnected to form a shift register connected to pins of the component. It is therefore possible, by adding a limited number of input/output pins, to record and to modify the communication signals carried by the conmiunication links. This technique makes it possible to debug the application cell. It has the drawback of disrupting the com- S munication links during movement of the information stored in the shift register because of the connections between these components.

When the test and emulation procedure is carried out, it is necessary to be able 25 to command the test cell in response to a particular state of the various input/output signals of the standard cell.

The American company MOTOROLA has drawn up for the DSP 96000 signal S' processor an emulation technique it calls "on-chip emulation". In this technique the signal processor is a standard cell to which is added a serial interface enabling cxecution to be resumed after a break point and loading of an instruction by means of a set of registers and address comparators connected to the buses of the cell adapted to produce break points. The status of these buses can be read via the serial interface.

This solution does not cover the case of a circuit comprising also an application cell, but only the cases where the standard cell is an "open" processor meaning a processor whose instruction bus is accessible, or where the program memory is a RAM type 4 rewritable memory. It does not make it possible to read the information present on the buses independently of the operation of the standard cell.

A known arrangement provides a test cell comprising a shift register in which stored information can circulate without disrupting the communication links. This test cell can also be commanded in response to the status of the standard cell input/output signals.

However, when the integrated circuit has been fabricated by the manufacturer, an error may remain in the program memory, which is often a read only memory (ROM). Any such error in the memory cannot be corrected. To alleviate this drawback, some manufacturers add to the circuit an additional rewritable memory such as an EPROM or EEPROM, for example. This additional memory uses specific technology which can limit the performance of the circuit in terms of processing speed and which is not necessarily compatible with the technology of the remainder of the circuit.

An object of the present invention is to provide an integrated circuit comprising a standard cell, an application cell and a test cell in which it is possible to correct an error in the program memory without degrading performance using a technique which is compatible with the manufacture of the circuit.

The objective of the invention is therefore to disclose the means to be added to an integrated circuit comprising a standard cell and an application cell to enable testing and emulation under the same condi ions as if the circuit were in the form of discrete components assembled on a printed circuit board.

The integrated circuit in accordance with the invention comprises a standard cell, an application cell and a test cell designed in particular to store or to modify 25 from outside the integrated circuit the value of communication signals passing between said standard cell and said application cell, said standard cell executing instructions provided on an instruction bus by a program memory located in said applicationcell in response to an instruction address carried by an instruction address bus, the conductors of said buses constituting communication links, characterised in that said test cell comprises branching means for replacing at least one erroneous instruction from said program memory with a replacement instruction previously stored in said integrated circuit in response to a predetermined state of some at least of said communication links.

In the integrated circuit comprising a standard cell, an application cell and a test cell the test cell comprising for each of said communication links a scanning unit I t provided with a unit memory connected at some times at least to said links, the unit memories being interconnected to form a first shift register, said test cell comprising also a second shift register provided with at least a first control register the outputs of which are each connected to a conductor of a first control bus, the integrated circuit advantageously comprises a comparator module to which are respectively connected the control bus and some at least of the communication links to produce a coincidence signal if the signals respectively supplied to it are identical.

Also, the integrated circuit comprising a standard cell, an application cell and a test cell, the standard cell operating in response to an operating mode signal, the latter comprises a trap circuit producing a trap signal for a predetermined state of the operating mode signal if the coincidence signal is present.

In a first embodiment of the integrated circuit comprising a standard cell, an application cell and a test cell the branching means comprising a substitution memory the last instruction that can be executed in which is an instruction to return to the 15 program memory and a trap multiplexer the output of which is connected in place of the instruction bus in the standard cell, a first input of which selected by the trap signal receives an instruction to branch to the substitution memory and the second input of which selected in the absence of the trap signal is connected to the instruction bus.

In a first variant of the integrated circuit comprising a standard cell, an application cell and a test cell the substitution memory is accessed by the instruction ad- S dress bus by means of a decooor circuit, writing and reading being effected by means of the scanning units of the first shift register associated with the instruction bus.

In a second variant of the integrated circuit comprising a standard cell, an ap- 25 plication cell and a test cell the substitution memory is accessed diectly by the standard cell, writing and reading being commanded by two further states of the operating mode signal.

In a second embodiment of the integrated circuit comprising a standard cell, an application cell and a test cell the scanning units associated with the instruction bus whose communication links each comprise an input channel and an output channel each comprise a first multiplexer the first input of which is connected to the input channel, the output of which is connected to the output channel and the control input of which receives the trap signal, a second multiplexer the second input of which is connected to the input channel and the output of which is connected to the input of a unit memory having its output connected to the second input of the first multiplexer, the first shift register comprising the succession of unit memories each connected to the first input of the second multiplexer of the next scanning unit, the output signals of the unit memories previously loaded by means of the first shift register forming the replacement instruction and then replacing the erroneous instruction following the appearance of the trap signal.

Also, in the integrated circuit comprising a standard cell, an application cell and a test cell the scanning unit further comprises a memory circuit whose data input is connected to the output of said unit memory and whose synchronisation input receives a trigger signal, the second input of said first multiplexer being connected not to the output of the unit memory but rather to the output of the memory circuit.

In order that the invention may be readily carried into effect, embodiments thereof will now be described in relation to the drawings, in which: Figure 1 is a block diagram of the integrated circuit in accordance with the 15 invention; Figure 2 is a block diagram of this circuit showing the test cell in more a.

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a a a a a detail; Figure 3 is a block diagram of a scanning module of the test cell; Figure 4 shows a first embodiment of a scanning unit of a scanning module; Figure 5 shows a second embodiment of a scanning unit of a scanning module; Figure 6 shows a third embodiment of a scanning unit of a scanning module; Figure 7 is a block diagram of the integrated circuit in accordance with the invention in which the test cell has additional features; Figure 8 is a block diagram of the registers of this test cell; Figure 9 is the block diagram of a known standard cell; Figure 10 is the block diagram of a standard cell modified in accordance with the invention; Figure 11 is the block diagram of a variant standard cell in accordance with the invention; Figure 12 shows a detail of the integrated circuit in accordance with the invention.

Components present in more than one figure are always identified by the same reference symbol.

Before describing the invention itself, the design of the various known parts of the integrated circuit will be outlined as this is essential to a proper understanding of the invention.

The integrated circuit 1 shown schematically in Figure 1 comprises an application cell 2 a test cell 3 and a standard cell 4, in particular a programmable unit such as a microprocessor, a signal processor or a more sophisticated circuit usually referred to as a microcontroller. The test cell 3 is disposed between the other two cells to monitor the signals exchanged between them. The latter two cells receive the same clock signal Ck.

The application cell 2 is connected by a link 21 to the exterior of the component 1. This link represents all input and output connections between this 15 cell and the device in which the component is incorporated. These ,o inputs/outputs therefore represent input/output pins. This cell is also connected to the test cell 3 by a first link communication L1 which, apart from the 99 *oo: invention, would be connected direct to the standard cell 4. This first communication link therefore represents all connections between the standard 20 cell and the application cell to be monitored. It may comprise control buses or write, read, synchronisation, interrupt, etc. links.

9. 9 *°oi The standard cell 4 is connected to the test cell 3 by a second 9ooo., 9 9 communication link L2 which, apart from the invention, would be the same as 9 9 the first communication link L1.

The test cell 3 receives command signals and modification information via a test link 31 and produces information on the status of the communication signals carried by the communication links on an observation link 32. In the normal operating mode of the integrated circuit 1 the test cell establishes the connection between these communication links and can store the communication signals without modifying them. It is as if it did not exist as far as the standard cell and the application cell are concerned. In the test or emulation operating mode of the integrated circuit the test cell can inject data received over the test link 31 into one or other of the communication links L1, 7a L2.

The test cell 3 will now be described in more detail with reference to Figure 2. In this embodiment the program memory of the standard cell 4 is part of the application cell 2. It produces the instruction at the location identified by an instruction address.

The two communication links L1, L2 which carry the communication signals are made up of a number of communication buses.

Scanning modules connect a bus of the first communication link L1 to the corresponding bus of the second communication link L2. The various scanning modules and the various communication buses are listed in the following table.

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o* 0 o Scanning Link LI Link L2 module Instruction address bus 3A 3A2 3A4 Instruction bus 3B 3B2 3B4 Monitor input bus 3C 3C2 3C4 Data bus 3D 3D2 3D4 Monitor output bus 3E 3E2 3E4 Data address bus 3F 3F2 3F4 All the buses are unidirectional except for the bidirectional data buses 3D2, 3D4.

The scanning modules comprise a unit memory for each conductor of the associated bus. These unit iemories a ar arranged to form a shift register whose input receives a substitution signal 39 over the test link 31 and whose output is connected S 15 to the observation link 32. The scanning modules further receive a synchronisation signal 34 also carried by the test link 31.

The links 3AB, 3BC, 3CD, 3DE, 3EF between the various scanning modules which form the shift register are identified by three characters, the first being the digit 3, the second being the reference letter of the input side scanning module and the third being the reference letter of the output side scanning module.

On each pulse of the synchronisation signal 34 all of the data stored in the shift register is advanced by one bit, a new input bit being provided by the substitution signal and the output bit being placed on the observation link 32.

The construction of the scanning module will be described in more detail 25 later. Their functions will now be described.

The first scanning module 3A imposes an instruction address by injecting into the instruction address bus 3A2 of the first communication link Ll the data stored in its unit memories. It can also store in these memories the instruction address supplied by the standard cell 4 on the corresponding instruction address bus 3A4.

The second scanning module 3B imposes an instruction by injecting into the instruction bus 3B4 of the second communication link L2 the data stored in its unit memories. It can also store in these memories the instruction provided by the application cell 2 on the corresponding instruction bus 3B2.

The third scanning modue 3C imposes a monitor signal by injecting into the monitor input bus 3C4 of the second communication link L2 the data stored in its unit memories. It can also store in these memories the monitor signals provided by the application cell 2 on the relevant monitor input bus 3C2. The monitor signals may be interrupts, indications, bus requests and reset requests, for example.

The fourth scanning module 3D associated with the bidirectional data buses 3D2, 3D4 imposes or stores data on each of these buses using its unit memories.

The fifth scanning module 3E imposes a monitor signal by injecting into the monitor output bus 3E2 of the first communication link LI the data stored in its unit memories. It can also store in these memories monitor signals produced by the standard cell on the relevant monitor output bus 3E4. The monitor signals can be write signals, read signals, signals to activate other buses, etc.

The sixth scanning module 3F imposes a data address by injecting into the data address bus 3F2 of the first communication link LI the information stored in its unit memories. It can also store in these memories the data address produced by the standard cell 4 on the relevant data address bus 3F4.

15 The six scanning modules are so designed that informaation can be routed in the shift register without modifying any of the signals present on the various buses, *e as will emerge more clearly as the description proceeds.

o: The first scanning module 3A will now be described in more detail with reference to Figure 3. The two instruction address buses 3A2, 3A4 of the first and second communication links LI and L2 each comprise eight conductors identified by the reference symbol of the bus of which they form part with a subscript between I and 8: 3A4, through 3A4 8 and 3A2, through 3A2 8 The scanning module 3A comprises one scanning unit for each pair of conductors with the same subscript. The eight scanning units are identified by a reference symbol comprising the letter A fol- 25 lowed by a digit which is the same as the subscript of the conductors of the buses with which they are associated. Each scanning unit receives the synchronisation signal 34.

The first scanning unit A receives the substitution signal 39 and produces a first o .w transfer signal A12 addressed to the second scanning unit. The second scanning unit A2 produces a second transfer signal A23 addressed to the third scanning unit, and so on up to the eighth scanning unit 3 which receives a seventh transfer signal A78 and is connected to the second scanning module 3B by the first link 3AB.

The first scanning unit Al is shown in Figure 4 in an embodiment which must not be regarded as limiting on the invention. It comprises a first multiplexer M1 whose 0 input is connected to an input channel of this unit which is the first conductor 3A4, of the instruction address bus 3A4 of the second communication link L2, whose I input is connected to the output of a memory circuit R, whose control input receives a first selection signal 35 carried by the test link 31, and whose output is connected to the first conductor 3A2 of the instruction address bus 3A2 of the first communication link L1 which is the output channel of the unit. It comprises a second multiplexer M2 whose 0 input receives the substitution signal 39, whose 1 input is connected to the 0 input of the first multiplexer M1, whose control input receives a second selection signal 38 and whose output is connected to the input of a unit memory DFF. This unit memory is a D type flip-flop, for example. It produces an output signal which takes the value that the signal applied to its data input had at the time of the P..vious rising edge applied to its synchronisation input. Its synchronisation input receives the synchronisation signal 34 and its output produces the first transfer signal A12. The scanning unit further comprises a memory circuit R in the form of a latch, for example. It transmits the data input state direction to o, its output during the time interval in which its synchronisation input is low. During 15 the time interval in which this synchronisation input is high, it transmits to its output o the value that the signal applied to its data input had at the time of the previous rising edge applied to its synchronisation input. It receives the first transfer signal A12 on its data input, a trigger signal 37 carried by the test link 31 on its synchronisation input and its output is connec"ld to the I input of the first multiplexer Ml, as already described.

The trigger signal 37 reproduces the output state of the u',it memory DFF at the output of the memory circuit R.

Depending on the values of the two selection signals 35, 38, the following operations are carried out: 25 the first and second multiplexers MI and M2 are switched to their 0 inputs, the unit memory DFF which is the first element of the shift register, as will emerge later, can transmit the substitution signal 39 to its output in response to the synchronisation signal 34, the first conductors 3A4 and 3A2, are connected together and isolated from the remainder of the scanning unit, so that the shift register can be advanced without modifying the operation of the standard cell 4 or the application cell 2, the first and second multiplexers MI and M2 are respectively switched to their 0 and 1 inputs, the unit memory DFF can store the signal present on the first conductor 3A4 of the instruction address bus 3A4 of the second communication link L2 in response to the synchronisation signal 34, the first conductors 3A4 3A2, being 11 connected together as in the previous situation, so that storage occurs without disruptio, the first and second multiplexers M1 and M2 are respectively switched to their 1 and 0 inputs, the first conductor 3A2 1 of the instruction address bus 3A2 of the second communication link is connected to the output of the memory circuit R and, as in the previous situation, the unit memory DFF can transmit the substitution signal to its output in response to the synchronisation signal 34, the first and second multiplexers M1 and M2 are switched to their 1 input, the first conductor CA2 1 of the instruction address bus 3A2 of the first communication link Li is connected to the output of the memory circuit R and the unit memory DFF can store the signal present on the first conductor 3A4 1 of the instruction address bus 3A4 of the second communication link L2.

Note that only this last situation justifies the presence of the memory circuit R in that it is necessary to store two items of information. In the other situations only one item of information requires to be stored and the unit Smemory is therefore sufficient. The invention is therefore equally applicable to the situation in which this memory circuit is dispensed with, the 1 input of the S. first multiplexer M1 being then connected direct to the output of the unit 2 memory DFF.

The second scanning unit is identical to the first, except as follows: .,-the 0 input and the output of its first multiplexer are respectively connected to the second conductors 3A4 2 3A2 2 of the instruction address buses 3A4, 3A2 of the second and first communication links L2 and L1, the 0 input of its second multiplexer receives the first transfer signal A12, its unit memory produces by way of output signal the second transfer signal A23.

The man skilled in the art will be readily able to transpose the foregoing modifications to define the inputs/outputs of the subsequent scanning units.

Thus the nth scanning unit differs from the first only in the following respects: the 0 input and the output of its first multiplexer are respectively connected to the nth conductors 3A4, 3A2, of the instruction address buses A/ 3A4, 3A2, 11a the 0 input of its second multiplexer receives the (n 1)th transfer signal A(n 1) its unit memory produces by way of output signal the nth transfer signal A(n) (n except for the eighth scanning unit for which the output signal is injected into the first link 3AB.

S S The second scanning module 3B is identical to the first scanning module 3A except that the instruction address buses 3A4, 3A2 of the second and first communication links L2 and LI are respectively replaced with the instructon buses 3B2, 3B4 of the first and second communication links LI and L2, the substitution signal 39 is replaced by the signal present on the first link 3AB and the first link is replaced by the second link 3BC.

The man skilled in the art will be able readily to transpose these modifications to obtain a full definition of the subsequent scanning modules, except that the third scanning module 3D is connected to bidirectional buses.

The sixth scanning module 3F is different in the sense that it is connected to the observation link 32 rather than a circulation link.

It will be assumed initially that the data buses 3D2, 3D4 are unidirectional, with the result that the fourth scanning module 3D is rendered identical to all the others. In this case, the shift register is obtained by connecting in series 15 all the unit memories of the test cell 3 along a circulation path by means of transfer 46, signals flowing within the same scanning unit and by means of circulation links to interconnect these units, when the second selection signal 38 switches the second multiplexer of each scanning unit to its 0 input. In this case the circulation path is a )4 electrically isolated from each bus conductor of the two communication links L1, L2.

The shift register is commanded by the synchronisation signal 34.

The special case of the fourth scanning module 3D will now be discussed.

This module is connected to two bidirectional data buses 3D2, 3D4 of the first and second communication links LI and L2 which each comprise 16 conductors, eight O*OIJ input conductors identified by the same reference signal as the buses of which they form part followed by an I and a subscript between 1 and 8: 3D21, through 3D21 8 and 3D41I through 3D4I1, and eight output conductors identified by the reference symbol of the bus of which they form part followed by an 0 and a subscript between 1 and 8: 3D20, through 3D20 and 3D40, through 3D40 The scanning module a B a I a 1 8 j comprises a scanning unit for each set of four conductors having the same subscript.

S* 30 The first scanning unit Dl associated with the conductors having the subscript I shown in Figure 5 comprises a first multiplexer M10 whose 0 input is connected to a first input channel of the unit which is the first input conductor 3D41, of the data bi, 3D4 of the second communication link L2, the 1 input of which is connected to the output of the memory circuit RO identical to that described previously, the control input of which receives the first selection signal 35 and the output of which is connected to the first input conductor 3D2I, of the data bus 3D2 of the first communication link L1 which is a second output channel of this unit. It comprises a second multiplexer M20 whose 0 and 2 inputs are connected to the third circulation link 3CD, whose 1 input is connected to the 0 input of the first multiplexer M whose 3 input is connected to a second input channel of this unit which is the first output conductor 3D20 of the data bus 3D2 of the first communication link LI, the two control inputs of which receive the second selection signal 38 and a third selection signal 36, and the output of which is connected to the input of a unit memory DFFO identical to that previously described. It further comprises a third multiplexer whose 0 input is connected to the 3 input of the second multiplexer M20, whose 1 input is connected to the output of the memory circuit RO, whose control input receives the first selection signal 35 and whose output is connected to the first output conductor 3D40, of the data bus 3D4 of the second communication link L2 which is the first output channel of this unit.

15 The unit memory DFFO of the scanning cell DI whose input is connected to the output of the second multiplexer M20 receives the synchronisation signal 34 on its synchronisation uaput and produces at its output a first transfer signal dl2 addressed to the second scanning unit D2.

The memory circuit RO of the first scanning cell Dl has its data input connected to the output of the unit memory DFFO, its synchronisation input receives S the trigger signal 37 and its output is connected to the 1 input of the first and third multiplexers MIO and The third selection signal 36 selects the input conductors or the output conductors by selecting either the group of inputs 0, 1 or the group of inputs 2, 3 of the seco..d multiplexer M20. In the former case, the second selection signal 38 selects the 0 or 1 input in the same way as for the second multiplexers of the scanning module and in the latter case it selects the 2 or 3 input according to whether it respectively selects the 0 or I input for the second multiplexers of these other modules.

The third multiplexer M30 has a function which is in all respects symmetrical with regard to the output conductor as that of the first multiplexer MI0 with regard to the input conductor. For this reason its operation does not need to be described in more detail.

The elements of a scanning unit of the fourth scanning module 3D which are added to the scanning unit of one of the other scanning modules having now been described, the operation will not be described in detail as it is identical to what has previously been described.

Also, the above remark concerning the memory circuit RO applies here also. Without departing from the scope of the invention, this circuit can be dispensed with provided that the 1 inputs of the first and third multiplexers MIO and M30 are connected direct to the output of the unit memory DDFO.

The second scanning unit D2 of the fourth scanning module 3D is identical to the first scanning unit D except as follows: the 0 input and the output of its first multiplexer are respectively connected to the second input conductor 3D412 of the data bus 3D4 of the second communication link L2 and to the second input conductor 3D21 2 of the data bus 3D2 of the first communication link LI, the 0 input and the output of its third multiplexer are respectively connected to the second output conductor 3D20 2 of the data bus 3D2 of the first com- 15 munication link L1 and to the second output conductor 3D20 2 of the data bus 3D4 of the second communication link L2, the 0 and 2 inputs of its second multiplexer receive the first transfer sig- 8 nal D12, its unit memory produces by way of output signal a second transfer signal D23.

The man skilled in the art will be able readily to transpose the foregoing modifications to define the inputs/outputs of the subsequent scanning units. Thus the nth scanning unit differs from the first as follows: the 0 input and the output of its first multiplexer are respectively connected to the nth input conductor 3D41 of the data bus 3D4 of the second communication link L2 and to the nth input conductor 3D21 of the data bus 3D2 of the first communication link LI, the 0 input and the output of its third multiplexer are respectively connected to the nth output conductor 3D20, of the data bus 3D2 of the first communication link LI and to the nth output conductor 3D40 of the data bus 3D4 of the second communication link L2, the 0 and 2 inputs of its second multiplexer receiver the (n l)th transfer signal d (n l)n, its unit memory produces by way of output signal the nth transfer signal D (n except for the eighth scanning unit for which the output signal is injected into the fourth circulation link 3DE.

It is clear that the replacement of a unidirectional scanning module such as the first scanning module 3A by a bidirectional module such as the fourth scanning module 3D does not modify in any way the shift register used to store and modify the signals carried by the communication links L1, L2.

It may be beneficial to define a bidirectional bus in the first communication link LI when the corresponding bus in the second communication link is unidirectional. This is the case, for example, with the instruction buses 3B2, 3B4 if the program memory in which these instructions are stored is a rewritable memory, in particular a RAM. In this case the content of this memory can be modified by the test cell 3.

S, Figure 6 shows one example of scanning unit for this application. This is the first scanning unit BI of the second scanning module 3B. The instruction bus 3B4 of the second communication link L2 is unidirectional and the bus 3B2 of the first communication link LI is bidirectional. The notation used previously is retained here. The scanning unit BI comprises a first multiplexer Mil whose 0 input is connected to an input channel of this unit which is the first output conductor 3B20, of the instruction bus 3B2 of the first communication link, the 1 input of which is connected to the output of a memory circuit RI identical to those previously described, the control input of which receives the first selection signal 35 and the output of which is connected to the first conductor 3B41 of the instruction bus 3B4 of the second communication link which is an output channel of this unit. It comprises a second multiplexer M21 whose 0 input is connected to the first circulation link 3AB, whose 1 input is connected to the 0 input of the first multiplexer Mll, whose control input receives the second selection signal 38 and whose output is connected to the data input of a unit memory DFFI identical to those previously described. Its unit memory DFFI receives on its synchronisation input the synchronisation signal 34 and produces at its output a first transfer signal B12. Its memory circuit RI receives the first transfer signal B12 on its data input, the trigger signal 37 on its synchronisation input and its output is connected direct to the first input conductor 3B2I of the instruction bus 3B2 of the first communication link 31 which is an auxiliary channel of this unit.

The operation of the scanning unit BI will not be described in more detail as it is readily deduced from that of the other two units previously described.

Moreover, the above remarks concerning the memory circuit RI apply here also. Without departing from the scope of the invention, this circuit can be dispensed with provided that the I input of the first multiplexer Ml 1 and the first input conductor 3B211 of the instruction 3B2 of the first communication link LI are connected direct to the output of the unit memory DFFI.

The various connections for full implementation of the test cell 3 will not be explained here either because the man skilled in the art will have no difficulty in implementing them by following the instructions given above with reference to the other types of scanning module.

There is defined in this way a test cell 3 which can store and modify the ib. various signals carried by the communication links LI, L2 using a shift register, the information stored in this register being shifted in relation to the exchange of signals between the standard cell 4 and the aplplication cell 2.

oNote moreover that it is possibl to verify that the information provided by the substitution signal 39 has not been degraded by the various scanning modules by analysing it on the observation link 32 as it progresses through the shift register.

According to a further aspect of the invention, the integrated circuit 1 is also designed to modify how the standard cell 4 operates in the case of a programmable unit such as a microprocessor. This interrupt requires a break condition and a break address to be supplied to the standard cell 4, as will be explained later. The two pieces of information are produced by control registers as shown in Figure 7.

P«o The test cell comprises the following additional components in this case: a break condition register 3G receiving at its input the substitution signal 39 and whose output is conected to a transmission link 3GH, a break address register 3H whose input is connected to the transmission link 3GH and whose output is connected to a supervisor link a clock switch 33 which sends the synchronisation signal 34 either to the various scanning modules 3A through 3F or to the two modules 3G, 3H according to whether a switching signal 33 carried by the test link 31 is in a first or a second state respectively, an output multiplexer which produces a certification signal 302 which takes the value at its input connected to the observation link 32 or at its input con- I I 17 nected to the supervisory link 30 according to whether the switching signal 33 is in its first or second state, respectively.

In this case, it is obviously the certification signal 302 which is connected to the exterior of the integrated circuit 1 instead of the observation link 32. When the switching signal 33 is in its first state, the test cell is equivalent to that previously described; when the switching signal 33 is in its second state, the test cell is equivalent to the set of two registers 3G, 3H.

The two registers 3G, 3H are shown in a particularly simple embodiment in Figure 8. The break condition register 3G is a set of eight unit memories MEI through ME8 of the same type as previously described. The outputs of these memories are each connected to a conductor of a break condition bus 3G4 which is connected to the standard cell 4. The data input of the first unit memory MEI receives the substitution signal 39 and the data input of each of the other memories is connected to the output of the previous unit memory. The synchronisation inputs of 15 these unit memories all receive a synchronisation signal 34.

The break condition bus 3G4 and the break address bus 3H4 are control buses.

The succession of unit memories of these two registers defines a second shift register of the same type as that formed by the scanning modules. It operates in the same way, with the same control signals, and alternately with the first, according to the status of the switching signal 33. It is used to communicate information to the standard cell 4 shown in Figure 9. Note that it is possible to verify that S" the information provided by the substitution signal 39 has not been degraded by these 4 registers by analysing it on the supervisory link 30 as it progresses through the second shift register.

The standard cell 4 comprises an operation module 4A and an instruction .0 module 4B provided with a sequencer and an instruction decoder, this being a "Harvard" type configuration.

The instruction module 4B receives over the instruction bus 3B4 an instruction from the address in the program memory that it produces on the instruction address bus 3A4. It is also connected to the control input bus 3C4. The sequencer operates synchronously with the clock signal Ck. The sequencer enables data to be exchanged between a data memory in the application cell 2 and the operation module 4A via the data bus 3D4 using the data address bus 3F4 and the data control bus 3E4. On each cycle the instruction decoder generates a control signal 4BA of the operation module which produces in return a situation signal 4AB addressed to the sequencer.

The modifications made to the standard cell 4 will now be described with reference to Figure 10. The operation module 4A of this cell is identical to the known modules in this type of device, which is one advantage of the invention.

In a manner that is also known, the instruction module 4B accesses the instruction address bus 3A4, the instruction bus 3B4, the control input bus 3C4, the control output bus 3G4 and the data address bus 3F4 and has an interrupt port for halting its operation. In the context of the invention, this module is further adapted to produce a status signal 4BD indicating the status of the sequencer and a progress status signal 43 indicating the progress of the instruction being executed. This information is particularly valuable when tile instruction is executed over a plurality of *o sequencer cycles, which is the case, for example, with data transfers when the data is r. routed over the data bus in a number of stages. It is further adapted to receive an 15 operating mode signal 4CBF defining its operation. This will be easy to do when the sequencer is specified and will not present any particular difficulty to the man skilled in the art. Consequently, the operation of this module will be explained with reference to this operating mode signal 4CBF immediately after the other component parts of the standard cell 4 have been described.

The standard, cell 4 comprises a decoder module 4C which receives an operation type signal 42 produced externally of the integrated circuit I on four wires, for example, and prozesses it to generate tile operating mode signal 4CBF such that the latter is in a format suitable for the instruction module 4B. This decoder module is ^t a simple interface.

The standard cell 4 also comprises a comparator module 4F which compared signals from the instruction module 4B and signals from the break condition register 30 and the break address register 3H to produce a coincidence signal 41 *oo when these are identical, for some states of the operating mode signal 4CBF. The coincidence signal 41 is applied to the interrupt port of the instruction module 4B.

In the example given here, the comparator module comprises a first comparator 4D which receives the status signal 4BD and compares it with the status of the break condition bus 3G4 and a second comparator 4E comparing the signals present on the instruction address bus 3A4 and the break address bus 3H4.

The operating mode signal 4CBF can assume various states including the following states which procure specific operation of the standard cell 4: first state: normal operation, the standard cell being equivalent to a known type cell and its operation being unmodified, second state: transfer of data present on the break condition bus 3G4 and the break address bus 3H4 to the comparator module 4F, third state: production of the coincidence signal 41 when the two comparators 4D, 4E have detected identical signals, fourth state: production of the coincidence signal 412 under the same conditions and interruption of operation of the instruction module 4B, fifth state: interruption of operation of the instruction module 4B on the instruction following the appearance of this state, sixth state: ,bQ step mode operation, interruption of operation of the instruction module 0* 4B after each instruction is executed, seventh state: execution of the instruction present on the instruction bus 3B4 and interruption of operation of the instruction module 4B, eighth state; return to operation of the instruction module 4B following an interrupt 0a a produced by another state.

As an optional feature, the comparator module 4F does not produce the coincidence signal 41 if the trigger signal 37 is present when the operating mode signal is in one of its fourth through seventh states, the effect of which is to prevent an interrupt from the instruction module 4B.

The modifications to the standard cell described above enable the test and emulation equipment to operate on the test cell 3 rcccording to the state of the signals to which the instruction module 4B has access, using the progress status signal 43 and the coincidence signal 41. This equipment can in particular produce the various signals carried by the test link 31 such as the three selection signals 35, 36, 38 and the trigger signal 37 in response to the coincidence signal 41. As the coincidence signal is produced at the start of execution of an instruction, the test and emulation equipment can trigger the storage of the signals present on the various buses connecting the standard cell 4 to the application cell 2 during or at the end of the instruction and interrupt the operation of the standard cell at the end of the instruction.

If the program stored in the program memory operates abnormally and does not reach a planned break point, it is therefore possible to interrupt execution of the program by producing the operating mode signal 4CBF in its fifth state. The status of the various buses and in particular that of the instruction address bus 3A4 is then accessible, which is not the case if the component is reset in the known manner.

It is also possible to store in the test cell 3 the status of all the buses connecting the standard cell 4 and the application cell 2 without modifying the operation of the instruction module 4B in response to the coincidence signal 41.

The invention naturally applies irrespective of the number of control registers and control buses, the comparator ,nodule 4F being designed accordingly.

The program memory of the standard cell 4 is usually a non-rewritable memory, for example a read only memory (ROM). In this case it is not possible to *000 correct a program error. In an alternative embodiment of the integrated circuit a rewritable substitute memory (RAM, for example) is added to this memory to enable any errors to be corrected. Figure 11 shows the substitution means which make it possible to replace a series of instructions from the program memory by a series of instructions from the substitution memory.

They comprise a trap circuit 41 which produces a trap signal 4HG for a ninth state of the operating mode signal 4CBF when the coincidence signal 41 is present. They also comprise a trap multiplexer 4G which produces on an additional instruction bus 4GB connected to the instruction module 4B in place of the instruction bus 3B4 a branch instruction 4GI if the trap signal 4HG is present and which V 6' connects the instruction bus 3B4 direct to the additional instruction bus 4GB otherwise. In the embodiment shown, which must not be regarded as limiting the invention in any way, the branch instruction 4GI is an unconditional branch 3o instruction from a hardwired circuit.

The substitution memory (which is not shown in the figure) can in a first configuration be accessed by the instruction address bus 3A4 using a decoder circuit switching the instruction address either to the program memory or to the substitution memory, according to the address format. As the technical means will be obvious to the man skilled in the art they will not be described in more detail here. Writing and reading may then be effected using the second scanning module 3B of the test cell 3.

In a second configuration the substitution memory can be accessed directly by the instruction module 4B in write mode and in read mode respectively for a tenth and an eleventh state of the operating mode signal 4B. In all cases, the last instruction from this memory that can be executed is an instruction to return to the program memory.

It is clear that using means similar to those described above and the knowledge of the man skilled in the art it is possible to implement a trap device capable of alleviating multiple errors in the program memory without departing from the scope of the invention.

If the error in the program memory is restricted to a single instruction, there is a simpler way to correct the error, as shown in Figure 12.

The second scanning module 3B is modified as follows to yield an auxiliary module 3B a: the first multiplexer of each scanning unit Bl through B8 of this S* 15 module is not controlled by the first selection signal 35 but rather by a signal which Soo is the logical sum of the first selection signal and the trap signal 4HG produced by 6:04 an OR logic operator, for example.

Also, the trap multiplexer 4G is dispensed with, the instruction bus 3B4 and the additional instruction bus 4GB being connected direct to each other.

It is therefore possible to replace an erroneous instruction with the information present at the output of the unit memories of the auxiliary scanning module 3B a.

The invention has been described with reference to an integrated circuit comprising five unidirectional buses each of eight conductors and one bidirectional bus of 16 conductors connecting the standard cell 4 and the application cell 2. It is not limited to this particular example and if a unit link between these two cells is defined as a communication link, that is to say a conductor of a unidirectional bus or 4: a pair of conductors of a bidirectional bus, it applies irrespective of the number of communication links and irrespective of how they are arranged. It goes without saying that the invention is also concerned with the case where the integrated circuits comprise multiple standard cells and/or multiple application cells, this latter term being understood in a very broad sense.

Claims (8)

1. An integrated circuit comprising a standard cell, an application cell and a test cell designed to store or to modify from outside the integrated circuit the value of communication signals passing between said standard cell and said application cell, said standard cell executing instructions provided on an instruction bus by a program memory located in said application cell in response to an instruction address carried by an instruction address bus, the conductors of said buses constituting communication links, wherein said test cell comprises branching means for replacing at least one erroneous instruction from said program memory with a replacement instruction previously stored in said integrated circuit in response to a predetermined state of some at least of said communication links, wherein said test cell comprises for each of said communication links a scanning unit provided with a unit memory selectably connectable to said links, said unit memories being interconnected to form a first o 15 shift register, said test cell including a second shift register provided with at S least a first control register the outputP of which are each connected to a conductor of a first control bus, said integrated circuit comprising a comparator 0 s module to which are respectively connected the control bus and some at least of the communication links to produce a coincidence signal if the signals 20 respectively supplied to it are identical.

2. An integrated circuit as claimed in claim 1, wherein said standard cell a operates in response to an operating mode signal, comprising a trap circuit a producing a trap signal for a predetermined state of said operating mode signal if said coincidence signal is present.

3. An integrated circuit as claimed in claim 2, wherein said branching means comprise a substitution memory the last instruction that can be executed in which is an instruction to return to said program memory, a trap multiplexer the output of which is connected in place of said instruction bus in said standard cell, a first input of which selected by said trap signal receives an instruction to branch to said substitution memory and the second input of which selected in the absence of said trap signal is connected to said instruction bus.

4. An integrated circuit as claimed in claim 3, wherein said substitution memory is accessed by said instruction address bus by means of decoder circuit and writing and reading are effected by means of said scanning units of said first shift regiister associated with said instruction bus.

An integrated circuit as claimed in claim 3, wherein said substitution memory is accessed directly by said standard cell and writing and reading are commanded by two further states of said operating mode signal.

6. An itegrated circuit as claimed in claim 2, wherein said scanning units associated with said instruction bus whose communication links each comprise an input channel and an output channel each comprise a first multiplexer the first input of which is connected to said input channel, the output of which is connected to said output channel and the control input of which receives said trap signal, a second multiplexer the second input of which is connected to said input channel and the output of which is connected to the input of a unit memory having its output connected to the second input of said first multiplexer, S said first shift register comprising the succession of said unit memories each *I 15 connected to the first input of the second multiplexer of the next scanning unit, the output signals of said unit memories previously loaded by means of said first shift register forming said replacement instruction and then replacing said o erroneous instruction following the appearance of said trap signal.

7. An integrated circuit as claimed in claim 6, wherein said scanning unit 20 further comprises a secondary memory circuit whose data input is connected to o• the output of said unit memory -!nd whose synchronisation input receives a e• trigger signal and the second input of said first multiplexer is connected not to S: the output of said unit memory but instead to the output of said secondary memory circuit.

8. An integrated circuit substantially as herein described with reference to Figures 1 8, and 10 12 of the accompanying drawings. DATED THIS THIRTIETH DAY OF NOVEMBER 1993 ALCATEL N.V. ABSTRACT This invention concerns an integrated circuit comprising a standard cell an application cell and a test cell designed in particular to store or to modify from outside the integrated circuit the value of communication signals passing be- tween said standard cell and said application cell. The standard cell executing in- structions provided on an instruction bus (3B4) by a program memory located in the application cell in response to an instruction address carried by an instruction address bus (3A4), the conductors of said buses constituting communication links, the test cell comprises branching means for replacing at least one instruction from the program memory with an erroneous replacement instruction previously stored in the integrated circuit in response to a predetermined state of some at least of the communication links. Figure 2. 0 *ee: a S a es s 0 00 a Ce e ooo OO Sa Baea