AU628911B2 - Computer system memory performance improvement apparatus - Google Patents

Computer system memory performance improvement apparatus

Info

Publication number
AU628911B2
AU628911B2 AU48292/90A AU4829290A AU628911B2 AU 628911 B2 AU628911 B2 AU 628911B2 AU 48292/90 A AU48292/90 A AU 48292/90A AU 4829290 A AU4829290 A AU 4829290A AU 628911 B2 AU628911 B2 AU 628911B2
Authority
AU
Australia
Prior art keywords
memory
data
computer system
dasd
datasets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU48292/90A
Other languages
English (en)
Other versions
AU4829290A (en
Inventor
Roger Francis Warr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Storage Technology Corp
Original Assignee
Storage Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Storage Technology Corp filed Critical Storage Technology Corp
Publication of AU4829290A publication Critical patent/AU4829290A/en
Application granted granted Critical
Publication of AU628911B2 publication Critical patent/AU628911B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F2003/0697—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers device management, e.g. handlers, drivers, I/O schedulers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/31—Providing disk cache in a specific location of a storage system
    • G06F2212/312—In storage controller

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Debugging And Monitoring (AREA)
  • Storage Device Security (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU48292/90A 1988-12-29 1989-12-20 Computer system memory performance improvement apparatus Ceased AU628911B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US29262688A 1988-12-29 1988-12-29
US292626 1988-12-29

Publications (2)

Publication Number Publication Date
AU4829290A AU4829290A (en) 1990-08-01
AU628911B2 true AU628911B2 (en) 1992-09-24

Family

ID=23125480

Family Applications (1)

Application Number Title Priority Date Filing Date
AU48292/90A Ceased AU628911B2 (en) 1988-12-29 1989-12-20 Computer system memory performance improvement apparatus

Country Status (5)

Country Link
EP (1) EP0451196A4 (fr)
JP (1) JPH04502527A (fr)
AU (1) AU628911B2 (fr)
CA (1) CA2006836C (fr)
WO (1) WO1990007746A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5491810A (en) * 1994-03-01 1996-02-13 International Business Machines Corporation Method and system for automated data storage system space allocation utilizing prioritized data set parameters
JP3641872B2 (ja) * 1996-04-08 2005-04-27 株式会社日立製作所 記憶装置システム

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4542458A (en) * 1982-05-21 1985-09-17 Hitachi, Ltd. Method of and apparatus for assigning software resources to memory devices

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4403286A (en) * 1981-03-06 1983-09-06 International Business Machines Corporation Balancing data-processing work loads
US4636946A (en) * 1982-02-24 1987-01-13 International Business Machines Corporation Method and apparatus for grouping asynchronous recording operations
US4633387A (en) * 1983-02-25 1986-12-30 International Business Machines Corporation Load balancing in a multiunit system
JPH06100981B2 (ja) * 1983-12-28 1994-12-12 株式会社日立製作所 記憶階層制御方式
US4603382A (en) * 1984-02-27 1986-07-29 International Business Machines Corporation Dynamic buffer reallocation
US4680703A (en) * 1984-06-25 1987-07-14 International Business Machines Corp. Data processing system with reorganization of disk storage for improved paging
JPS61114363A (ja) * 1984-11-07 1986-06-02 Hitachi Ltd 計算機システム間ジヨブ転送方式

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4542458A (en) * 1982-05-21 1985-09-17 Hitachi, Ltd. Method of and apparatus for assigning software resources to memory devices

Also Published As

Publication number Publication date
WO1990007746A1 (fr) 1990-07-12
CA2006836C (fr) 1995-08-29
EP0451196A1 (fr) 1991-10-16
EP0451196A4 (en) 1992-12-23
AU4829290A (en) 1990-08-01
JPH04502527A (ja) 1992-05-07
CA2006836A1 (fr) 1990-06-29

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