AU6154999A - High efficiency switched gain power amplifier - Google Patents

High efficiency switched gain power amplifier Download PDF

Info

Publication number
AU6154999A
AU6154999A AU61549/99A AU6154999A AU6154999A AU 6154999 A AU6154999 A AU 6154999A AU 61549/99 A AU61549/99 A AU 61549/99A AU 6154999 A AU6154999 A AU 6154999A AU 6154999 A AU6154999 A AU 6154999A
Authority
AU
Australia
Prior art keywords
signal
power amplifier
amplifier
switch
path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
AU61549/99A
Other versions
AU772636B2 (en
Inventor
Richard J. Camarillo
Darin Hunzeker
Ralph Kaufman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/158,456 external-priority patent/US6060949A/en
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of AU6154999A publication Critical patent/AU6154999A/en
Application granted granted Critical
Publication of AU772636B2 publication Critical patent/AU772636B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0088—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using discontinuously variable devices, e.g. switch-operated
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
    • H03F3/602—Combinations of several amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H03F2203/7239—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers and shunting lines by one or more switch(es)

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Transmitters (AREA)
  • Mobile Radio Communication Systems (AREA)

Description

WO 00/18005 PCT/US99/21758 1 HIGH EFFICIENCY SWITCHED GAIN POWER AMPLIFIER BACKGROUND INFORMATION 5 I. Field of the Invention The present invention relates generally to power gain control for a power amplifier and particularly to a wireless communication device, such as a CDMA wireless phone. 10 II. Description of the Related Art In many electronic environments, such as most hand-held communication systems including code-division-multiple-access (CDMA) or any form of time-division-multiple access (TDMA) 15 technology, RF power output from a mobile unit varies in large dynamic ranges. In a CDMA radiotelephone system, multiple signals are transmitted simultaneously at the same frequency. The signals are spread with different digital codes, thus allowing detection of the desired signal while the unintended signals appear as noise or interference to the 20 receiver. Spread spectrum systems can tolerate some interference, and the interference added by each new mobile station increases the overall interference in each cell site. Each mobile station introduces a unique level of interference, which depends on its received power level at the cell site. 25 The CDMA system uses power control to minimize mutual interference. A precise power control is critical to avoid excessive transmitter signal power that is responsible for contributing to the overall interference of the system. Power of the individual mobile stations varies with the distance between the mobile station and the base 30 station and the number of other subscriber mobile stations in that base station or sector.
WO 00/18005 PCT/US99/21758 2 In a typical hand-held wireless unit, the power amplifier is biased class AB to reduce power consumption during periods of low transmit power, but power continues to be consumed. Typically an isolator is used to isolate the power amplifier from the effects of load impedance in 5 subsequent stages. One method to avoid continuous battery draw is to employ a means to bypass the amplifier with switches, and then remove DC power from the Amplifier. This method is illustrated in FIG. 7. A power amplifier circuit 8 is shown with a power amplifier 32 and an isolator 55. An RF input 12 having an RF-signal to be amplified is 10 connected to a pole of a first switch 20. When the amplifier is on, the switch 20 connects the RF-input 12, via path 28, to an input of power amplifier 32. The RF-signal is amplified and output to the isolator 55, and then transmitted through the second switch 42 to the RF-output 54 of the power amplifier circuit 8. To bypass the power amplifier 32, the first 15 switch 20 connects the RF-input 12 to the bypass path 30 and the second switch 42 transmits the signal to the RF-output 54. The drawback of this technique is that the amplifier must overcome the added switching loss during times that higher transmit power is required. This can tend to cancel the benefits of bypassing. Furthermore, using a switch and an 20 isolator requires more power to operate and is more costly to build. FIG. 6 illustrates a prior art power amplifier circuit. An analog signal is fed from a driver amplifier 280 through a band pass filter 298 to a first switch 20. The switch 20 alternates between a bypass path 30 and an amplifier path 28, wherein a power amplifier 32 amplifies the signal. A 25 second switch 42 connects the analog signal from either the bypass path 30 or the output of amplifier 32 to a circulator 55, which routes the signal to the RF-output port 54.
WO 00/18005 PCT/US99/21758 3 SUMMARY OF THE INVENTION What is needed in the art is a power amplifier circuit which conserves more power and which is less complex and expensive to build 5 by making better use of the isolator, thereby allowing removal of a second switch located after the power amplifier. An object of the present invention is to increase the efficiency of power amplifier usage by using the termination port of an isolator as the combining mechanism for the bypass network, the power amplifier 10 output, and the RF-output port. With this configuration, an output switch becomes unnecessary. Another object of the present invention is to provide an improved power amplifier which requires less parts and is less complex to build. Yet another object of the present invention is to provide an 15 improved power amplifier which is less costly to build. These objects and others may be realized by the invention disclosed herein. In a power amplifier circuit, a bypass network is provided to bypass the power amplifier in the circuit when the amplifier gain is not required. During these periods of low power operation, the 20 amplifier is turned off. The bypass network consists of a bypass path, and an attenuation path. The attenuation path allows variability through use of an external resistor, and the bypass path allows no variability. Switches operate to control the flow of the signal to the amplifier, or through either the bypass path or the attenuation path. The signal from 25 the bypass network is input to a circulator, which routes the signal to the port connected to the output of the power amplifier. Because the power amplifier is turned off during periods when the bypass is used, it appears to be a very large impedance to the signal. Most of the input power signal is reflected back to the circulator for a normal exit from the RF-out port. 30 An external resistor is used in conjunction with the attenuated path to provide flexibility in the available gain steps.
WO 00/18005 PCTIUS99/21758 4 In another aspect of the present invention, the band pass filter is placed in the amplification path such that filtering is bypassed when the power amplifier is bypassed. This reduces the gain step size when changing modes from amplification to bypass. The driver amplifier 5 therefore becomes the output amplifier and the filter following the amplifier circuitry operates to remove any undesired spurs. In another aspect of the present invention, when bypassing the power amplifier, it becomes possible to drive the driver amplifier harder and thus provide greater flexibility in choosing gain steps. 10 BRIEF DESCRIPTION OF THE DRAWINGS The features and advantages of the present invention will become more apparent from the detailed description set forth below when taken 15 in conjunction with the drawings in which like reference characters correspond throughout and wherein: FIG. 1 is a plan drawing of the first embodiment of the present invention; FIG. 2 provides a block diagrammatic representation of a mobile 20 station spread spectrum transmitter in which may be incorporated an efficient power amplifier of the present invention; FIG. 3 shows an exemplary implementation of an RF transmitter included within the spread spectrum transmitter of FIG. 2; FIG. 4 is a plan drawing of a second embodiment of the present 25 invention; FIG. 5 is a plan drawing of a third embodiment of the present invention; FIG. 6 is a plan drawing of a prior art amplifier circuit; and FIG. 7 is a plan drawing of a prior art power amplifier circuit. 30 WO 00/18005 PCT/US99/21758 5 DETAILED DESCRIPTION OF THE INVENTION FIG. 1 is a schematic diagram showing the broad concept of the invention. A power amplifier circuit, indicated generally by reference 5 numeral 10 comprises a power amplifier 32, a circulator 52, a series of switches, 20, 24 and 42, and bypass paths 34 and 36 around the power amplifier 32. An RF-input 12 having an RF-signal to be amplified is connected to a pole of first switch 20. When the power amplifier is turned on and power amplification is required, the switch 20 connects the 10 RF-input 12, via a path 28, to an input of power amplifier 32. The RF signal is amplified and output from the power amplifier toward the circulator 52. The circulator 52 routes the signal to port of the RF-output 54 of power amplifier circuit 10. When the power amplifier is not needed and turned off, the 15 switch 20 switches the signal path to a bypass network 48 comprising a bypass path 36 and an attenuated path 34. To send the signal through the bypass path 36, switches 24 and 42 switch to a first position such that the signal flows through bypass path 36. Switches 24 and 42 can also switch the signal to flow through the attenuated path 34. From switch 42 the 20 signal is transmitted to an input of circulator 52. The circulator 52 routes the signal to the port connected to the output 50 of the power amplifier 32. The output of the power amplifier 50 appears as a high impedance to the signal and thus the signal is reflected back to the circulator 52, which routes the signal to the port of the RF-output 54 of amplifier circuit 10. 25 FIG. 2 is a schematic diagram illustrating the use of the power amplifier of the present invention in the signal processing circuitry of a mobile station. In an exemplary CDMA system, orthogonal signaling is employed to provide a suitable ratio of signal to noise on the mobile station-to-base station link, or the "reverse" channel. Data bits 200 30 consisting of, for example, voice converted to data by a vocoder, are supplied to an encoder 202 where the bits are convolutionally encoded. When the data bit rate is less than the bit processing rate of the encoder WO 00/18005 PCT/US99/21758 6 202, code symbol repetition may be used such that the encoder 202 repeats the input data bits 200 in order to create a repetitive data stream at a bit rate which matches the operative rate of the encoder 202. In an exemplary embodiment the encoder 202 receives data bits 200 at a 5 nominal bit rate (Rb) of 11.6 kbits/second, and produced Rb /r = 34.8 symbols/second, where "r" denotes the code rate (e.g. 1/3) of the encoder 202. The encoded data is then provided to block interleaver 204 where it is block interleaved. With the 64-ary orthogonal modulator 206, the symbols are 10 grouped into characters containing log 2 64 = 6 symbols at a rate of (1/r)( Rb/log 2 64) = 5,800 characters/second, with there being 64 possible characters. In a preferred embodiment each character is encoded into a Walsh sequence of length 64. That is, each Walsh sequence includes 64 binary bits or "chips", there being a set of 64 Walsh codes of length 64. 15 The 64 orthogonal codes correspond to Walsh codes from a 64 by 64 Hadamard matrix wherein a Walsh code is a single row or column of the matrix. The Walsh sequence produced by the modulator 206 is provided to an exclusive-OR combiner 208, where it is then "covered" or multiplied 20 at a combiner with a PN code specific to a particular mobile station. Such a "long" PN code is generated at a rate Rc by a PN long code generator 210 in accordance with a user PN long code mask. In an exemplary embodiment the long code generator 210 operates at an exemplary chip rate, Re, of 1.2288 Mhz so as to produce four PN chips per Walsh chip. 25 The output of the exclusive -OR combiner 208 is split into identical signals A and B. Signals A and B are input into the exclusive-OR combiners 256 and 254 of FIG. 3 as described below. FIG. 3 is a schematic diagram showing an exemplary implementation of the RF transmitter 250 in a mobile station. In CDMA 30 spread spectrum applications, a pair of short PN sequences, PNI and PNQ, are respectively provided by a PN, generator 252 and a PNQ generator 254 to exclusive-OR combiners 256 and 258, along with the output A and B WO 00/18005 PCT/US99/21758 7 from exclusive-OR combiner 208 of FIG. 2. The PNI and PNQ sequences relate respectively to in phase (I) and quadrature phase (Q) communication channels, and are generally of a length (32,768 chips) much shorter than the length of each user long PN code. The resulting I 5 channel code spread sequence 260 and Q-channel code spread sequence 262 are then passed through baseband filters 264 and 266, respectively. Digital to Analog (D/A) converters 270 and 272 are provided for converting the digital I-channel and Q-channel information, respectively, into analog form. The analog waveforms produced by D/A converters 10 270 and 272 are provided with a local oscillator (LO) carrier frequency signals Cos (2nft) and Sin (2itft), respectively, to mixers 288 and 290 where they are mixed and provided to summer 292. The quadrature phase carrier signals Sin (2nft) and Cos (21rft) are provided from suitable frequency sources (not shown). These mixed IF signals are summed in 15 summer 292 and provided to mixer 294. Mixer 294 mixes the summed signal with an RF frequency from frequency synthesizer 296 so as to provide frequency upconversion to the RF frequency band. The RF may then be bandpass filtered 298 and provided to an efficient parallel stage RF amplifier 10 of the invention. 20 The filter 298 removes undesired spurs caused from upconversion 296. A similar filter (not shown) may be located following the amplifier circuitry to remove undesired spurs when the circuit is operating in bypass mode. In a bypass mode, the previous driver amplifier becomes the output amplifier and filtering may be necessary to prevent extra spurs 25 from mixing in the non-linearities of the amplifier. This filtering may be accomplished by the similar filter (not shown), thus the band-pass filter 298 may be located in the amplification path as illustrated in FIGS. 4 and 5 discussed below. This also increases flexibility in choosing gain steps. FIG. 4 is a second embodiment of the present invention wherein 30 the analog signal is switched 20 between a bypass path 30 and an amplifier path 28. However, band-pass filtering 298 only occurs in the amplifier WO 00/18005 PCT/US99/21758 8 path 28. Accordingly, the signal is band-pass filtered 298 and fed to the power amplifier 32, amplified, and transmitted to the circulator 55, which routes the signal towards the RF-output port 54. The circulator 55 is connected to ground through a switch 43 and a resistor 45 and the output 5 port 54 of the circuit when the first switch 20 directs the analog signal through the amplifier path. Accordingly, with this configuration, when reflected or returned RF signals enter the circulator 55 from the direction of the RF-output port 54, the reflected signal is routed by the circulator 55 to ground. When the first switch 20 switches the analog signal to the 10 bypass path 30, the second switch 43 connects the bypass path 30 to the circulator 55, and the signal is routed toward the output of the amplifier. This will appear as a high impedance, reflecting the signal back through isolator 55 and to RF-output port 54. When high output power is not needed, the power amplifier 32 is 15 turned off and the first switch 20 switches to the bypass path 30, whereby the power amplifier 32 is bypassed and the driver amplifier 280 operates as the power amplifier. The second switch 43 connects the bypass path 30 to the circulator 55. The input signal in this mode is routed through the bypass path 30 to the circulator 55. The signal is routed by the circulator 20 to the output of the power amplifier 32, and is reflected back through the isolator 55 and to the output of the RF-output port 54. FIG. 5 shows a third embodiment of the present invention having a driver amplifier 280 and a band-pass filter 298 for filtering the amplified signal before a first switch 20. The output from the band pass filter 298 is 25 switched by the first switch 20 which switches between an amplifier path 28 and a bypass path 30. The power amplifier 32 in the amplifier path amplifies and transmits the signal to a circulator 55, which routes the signal towards an RF-output port 54. The first switch 20 alternates between transmitting the filtered signal to the amplifier path 28 or the 30 bypass path 30. A second switch 43 in the bypass path is included which connects the circulator 55 to ground through a resistor 45 in a first mode, WO 00/18005 PCT/US99/21758 9 and connects the circulator 55 to the bypass path 30 in a second mode. The resistor 45 may have a value of 50 ohms, for example. Any feedback or return signal from the RF-output port 54 is routed to ground when the second switch 43 is in the second mode. When in 5 the first mode switch 20 transmits the signal to the bypass path 30, switch 43 transmits the signal from the bypass path 30 to the circulator 55. The circulator 55 routes the signal to the output of the power amplifier, which appears to be a large impedance and reflects most of the signal back to the circulator 55. The signal is then routed toward the RF-output port 54. 10 Accordingly, the switch 43 adds isolation due to the fact that the signal cannot be switched to an attenuation path. This embodiment is applicable when only one gain step is desired. The previous description of the preferred embodiments is provided to enable any person skilled in the art to make or use the 15 present invention. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the inventive faculty. Thus, the present invention is not intended to be limited to the embodiments shown herein, but is to be accorded the 20 widest scope consistent with the principles and novel features disclosed herein. WHAT IS CLAIMED IS:

Claims (51)

1. A power amplifier circuit arrangement, comprising: 2 a power amplifier having an input and an output; an RF-input port; 4 an RF-output port; means for bypassing the power amplifier through a bypass 6 network; first means for switching an RF-signal from the RF-input 8 port between the bypass network and the input to the amplifier; and 10 a circulator connecting the bypass network, the output of the power amplifier, and the RF-output port, whereby the RF 12 signal inputted from the bypass network to the circulator is routed to the output of the power amplifier and the RF-signal 14 inputted into the circulator from the power amplifier output is routed to the RF-output port.
2. The power amplifier circuit of claim 1 wherein when the 2 power amplifier is powered off, the first means for switching switches the RF-signal to the bypass network such that the RF 4 signal bypasses the power amplifier, routes through the circulator towards the power amplifier output, is reflected by the power 6 amplifier, and routes through the circulator to the RF-output port.
3. The power amplifier circuit of claim 1 wherein the bypass 2 network comprises a bypass path and an attenuated path and second means for switching between the bypass path and the 4 attenuated path. WO 00/18005 PCT/US99/21 7 5 8 11
4. The power amplifier circuit of claim 3 wherein the 2 attenuated path includes an external resistor connected to ground to allow flexibility in providing gain steps.
5. The power amplifier circuit of claim 3 wherein when the 2 power amplifier is powered off and the first means for switching connects the RF-input port to the bypass network, and when the 4 first means for switching switches to the bypass path, the RF signal passes through the bypass path, routes through the 6 circulator toward the output of the power amplifier, is reflected by the power amplifier and routes through the circulator to the RF 8 output port.
6. The power amplifier circuit of claim 3 wherein when the 2 power amplifier is powered off and the first means for switching connects the RF-input port to the bypass network, and when the 4 second means for switching switches to the attenuated path, the RF-signal passes through the attenuated path, routes through the 6 circulator toward the power amplifier output, is reflected by the power amplifier and routes through the circulator to the RF 8 output port.
7. The power amplifier circuit of claim 4, wherein when the 2 power amplifier is powered on, and the first means for switching connects the RF-input port to the input of the power amplifier, 4 the second means for switching switches the attenuated path to the circulator to maximize reverse isolation and protect against 6 oscillation. WO 00/18005 PCT/US99/21758 12
8. The power amplifier circuit of claim 4, wherein the 2 external resistor is a variable resister for gain adjustment.
9. In a power amplifier circuit with an RF-input port and an 2 RF-output port, a bypass network, a circulator connected to the bypass network, the output of the power amplifier, and the RF 4 output, a method to maximize dynamic range comprising the steps of: 6 powering off the power amplifier; switching an RF-signal from the RF-input port to the 8 bypass network; routing the RF-signal from the bypass path toward the 10 power amplifier through the circulator; reflecting a substantial portion of the RF-signal incident to 12 the power amplifier output back to the circulator; routing the reflected RF-signal through the circulator to 14 the RF-output port.
10. A power amplifier circuit arrangement, comprising: 2 a driver amplifier for transmitting an RF analog signal; first means for switching said RF analog signal between a 4 bypass path and an amplifier path; a band pass filter positioned in said amplifier path which 6 filters said RF analog signal and produces a filtered signal; a power amplifier positioned in said amplifier path which 8 amplifies said filtered signal to produce an amplified signal; a circulator which routes said amplified signal to an RF 10 output port; said bypass path connecting an output of said driver 12 amplifier to said circulator when said first means for switching WO 00/18005 PCT/US99/21758 13 switches to said bypass path, wherein said bypass path connects to 14 said circulator such that said RF analog signal input to said circulator from said bypass path is routed to said power amplifier; 16 second means for switching positioned in said bypass path and switching a connection to said circulator between said bypass 18 path and ground through a resistor, whereby, when said second means for switching connects to ground, power returned to the 20 circuit from the direction of the RF-output port is routed to ground to isolate said power amplifier circuit arrangement.
11. A power amplifier circuit arrangement, comprising: 2 a driver amplifier for transmitting an RF analog signal; a band pass filter positioned for filtering said RF analog 4 signal and produces a filtered signal; first means for switching said filtered signal between a 6 bypass path and an amplifier path; a power amplifier positioned in said amplifier path which 8 amplifies said filtered signal to produce an amplified signal; a circulator which routes said amplified signal to an RF 10 output port; said bypass path connecting an output of said band pass 12 filter to said circulator when said first means for switching switches to said bypass path, wherein said bypass path connects to 14 said circulator such that said filtered signal input to said circulator from said bypass path is routed to said power amplifier; 16 second means for switching positioned in said bypass path and switching a connection to said circulator between said bypass 18 path and ground through a resistor, whereby, when said second means for switching connects to ground, power returned to the 20 circuit from the direction of the RF-output port is routed to ground to isolate said power amplifier circuit arrangement. WO 00/18005 PCT/US99/21758 14
12. The power amplifier circuit arrangement of claim 11, 2 further comprising means for controlling said first and said means for switching.
13. The power amplifier circuit arrangement of claim 11, 2 wherein said resister is approximately 50 ohms.
14. The power amplifier circuit arrangement of claim 10, 2 wherein said first means for switching switches to said bypass path the power amplifier is turned off.
15. The power amplifier circuit arrangement of claim 11, 2 wherein said first means for switching switches to said bypass path the power amplifier is turned off.
16. A power amplifier circuit arrangement, comprising: 2 a driver amplifier for transmitting an analog signal; a first switch for selectively switching the analog signal 4 between a bypass path and an amplifier path, said amplifier path comprising: 6 a band-pass filter for filtering the analog signal and for producing a filtered signal; 8 a power amplifier for receiving the filtered signal and for producing an amplified signal; 10 a first hybrid circuit for splitting the amplified signal into an in-phase signal and a quadrature signal; and 12 a second hybrid circuit for inverting the in-phase signal to produce an inverted signal and for summing the 14 inverted signal and the quadrature signal to produce a summed signal, WO 00/18005 PCT/US99/21758 15 16 said bypass path connecting an output of said driver amplifier with an isolated port of said second hybrid circuit when 18 said first switch switches the analog signal to said bypass path, whereby the analog signal transmitted from said driver amplifier 20 will reflect off of said power amplifier and be routed to an output port.
17. The circuit arrangement of claim 1, further comprising: 2 a second switch positioned in said bypass path; and a terminating resistor connected to a pole of said second 4 switch, said second switch selectively connecting the isolated port 6 of said second hybrid circuit with either said first switch or said terminating resistor.
18. The circuit arrangement of claim 1, wherein the analog 2 signal is a radio-frequency analog signal.
19. The power amplifier circuit arrangement of claim 1, 2 wherein said first switch switches the analog signal to said bypass path when said power amplifier is turned off.
20. A power amplifier circuit arrangement, comprising: 2 a driver amplifier for transmitting an analog signal; a first switch for selectively switching the analog signal 4 between a bypass path and an amplifier path, said amplifier path comprising: 6 a band-pass filter for filtering the analog signal and for producing a filtered signal; 8 a power amplifier for receiving the filtered signal and for producing an amplified signal; WO 00/18005 PCT/US99/21758 16 10 a first hybrid circuit for splitting the amplified signal into an in-phase signal and a quadrature signal; and 12 a second hybrid circuit for inverting the quadrature signal to produce an inverted signal and for summing the inverted 14 signal and the in-phase signal to produce a summed signal, said bypass path connecting an output of said driver 16 amplifier with an isolated port of said second hybrid circuit when said first switch switches the analog signal to said bypass path, 18 whereby the analog signal transmitted from said driver amplifier will reflect off of said power amplifier and be routed to an output 20 port.
21. The circuit arrangement of claim 5, further comprising: 2 a second switch positioned in said bypass path; and a terminating resistor connected to a pole of said second 4 switch, said second switch selectively connecting the isolated port 6 of said second hybrid circuit with either said first switch or said terminating resistor.
22. The circuit arrangement of claim 5, wherein the analog 2 signal is a radio-frequency analog signal.
23. The power amplifier circuit arrangement of claim 5, 2 wherein said first switch switches the analog signal to said bypass path when said power amplifier is turned off.
24. A method for amplifying a signal in a circuit having a 2 driver amplifier, an amplifier path comprising a first switch, a band-pass filter, a power amplifier, a first hybrid circuit and a 4 second hybrid circuit, and a bypass path connecting an isolated WO 00/18005 PCT/US99/21758 17 port of the second hybrid circuit to the first switch, said method 6 comprising: (A) producing a driver signal from the driver amplifier; 8 (B) selectively switching the driver signal between the amplifier path and the bypass path using the first switch, 10 wherein when the driver signal is switched in said switching step to the amplifier path, said method further 12 comprises the steps of: (a) band-pass filtering the driver signal by the 14 band- pass filter to produce a filtered signal; (b) amplifying the filtered signal by the power 16 amplifier to produce an amplified signal; (c) splitting the amplified signal into an in-phase 18 signal and a quadrature signal in the first hybrid circuit; (d) inverting the in-phase signal to produce an 20 inverted signal in the second hybrid circuit; and (e) summing the inverted signal and the 22 quadrature signal to produce a summed signal in the second hybrid circuit, 24 and wherein when the driver signal is switched in said switching step to the bypass path, said method further comprises 26 the steps of: (a) turning off the power amplifier; 28 (b) transmitting the driver signal to the isolated port of the second hybrid circuit; 30 (c) reflecting the driver signal off an output of the power amplifier to an output port.
25. The method of claim 9, wherein the circuit further 2 comprises a second switch positioned in the bypass path, said method further comprising: WO 00/18005 PCT/US99/21758 -18 4 selectively switching the second switch between connecting the isolated port of the second hybrid circuit to a terminating 6 resistor and connecting the isolated port of the second hybrid circuit to the first switch.
26. The method for amplifying a signal of claim 9, wherein the 2 driver signal is a radio-frequency analog signal.
27. A method for amplifying a signal in a circuit having a 2 driver amplifier, an amplifier path comprising a first switch, a band-pass filter, a power amplifier, a first hybrid circuit and a 4 second hybrid circuit, and a bypass path connecting an isolated port of the second hybrid circuit to the first switch, said method 6 comprising: (A) producing a driver signal from the driver amplifier; 8 (B) selectively switching the driver signal between the amplifier path and the bypass path using the first switch, 10 wherein when the driver signal is switched in said switching step to the amplifier path, said method further 12 comprises the steps of: (a) band-pass filtering the driver signal by the 14 band- pass filter to produce a filtered signal; (b) amplifying the filtered signal by the power 16 amplifier to produce an amplified signal; (c) splitting the amplified signal into an in-phase 18 signal and a quadrature signal in the first hybrid circuit; (d) inverting the in-phase signal to produce an 20 inverted signal in the second hybrid circuit; and (e) summing the inverted signal and the 22 quadrature signal to produce a summed signal in the second hybrid circuit, WO 00/18005 PCT/US99/21758 19 24 and wherein when the driver signal is switched in said switching step to the bypass path, said method further comprises 26 the steps of: (a) turning off the power amplifier; 28 (b) transmitting the driver signal to the isolated port of the second hybrid circuit; 30 (c) reflecting the driver signal off an output of the power amplifier to an output port.
28. The method of claim 12, wherein the circuit further 2 comprises a second switch positioned in the bypass path, said method further comprising: 4 selectively switching the second switch between connecting the isolated port of the second hybrid circuit to a terminating 6 resistor and connecting the isolated port of the second hybrid circuit to the first switch.
29. The method for amplifying a signal of claim 12, wherein 2 the driver signal is a radio-frequency analog signal.
30. A power amplifier circuit arrangement, comprising: 2 a driver amplifier for transmitting an analog signal; a first switch for switching the analog signal between a 4 bypass path and an amplifier path, said amplifier path comprising: 6 a band pass filter which filters the analog signal to produce a filtered signal; 8 a first hybrid circuit for splitting the filtered signal into an in-phase signal and a quadrature signal; 10 a first power amplifier for amplifying the in-phase signal to produce a first amplified signal; WO 00/18005 PCT/US99/21758 20 12 a second power amplifier for amplifying the quadrature signal to produce a second amplified signal; and 14 a second hybrid circuit for inverting the first amplified signal to produce an inverted signal and for summing 16 the inverted signal and the second amplified signal, said bypass path connecting an output of said driver 18 amplifier and an isolated port of said second hybrid circuit when said first switch switches the analog signal to said bypass path.
31. A power amplifier circuit arrangement, comprising: 2 a driver amplifier for transmitting an analog signal; a first switch for switching the analog signal between a 4 bypass path and an amplifier path, said amplifier path comprising: 6 a band pass filter which filters the analog signal to produce a filtered signal; 8 a first hybrid circuit for splitting the filtered signal into an in-phase signal and a quadrature signal; 10 a first power amplifier for amplifying the in-phase signal to produce a first amplified signal; 12 a second power amplifier for amplifying the quadrature signal to produce a second amplified signal; and 14 a second hybrid circuit for inverting the second amplified signal to produce an inverted signal and for summing 16 the inverted signal and the first amplified signal, said bypass path connecting an output of said driver 18 amplifier and an isolated port of said second hybrid circuit when said first switch switches the analog signal to said bypass path.
32. The power amplifier circuit arrangement of claim 15, 2 wherein the analog signal is a radio-frequency analog signal. WO 00/18005 PCT/US99/21758 -21
33. The power amplifier circuit arrangement of claim 16, 2 wherein the analog signal is a radio-frequency analog signal.
34. The power amplifier circuit arrangement of claim 15, 2 wherein said switch switches to said bypass path when the power amplifier is turned off.
35. The power amplifier circuit arrangement of claim 16, 2 wherein said switch switches to said bypass path when the power amplifier is turned off.
36. The circuit arrangement of claim 15 further comprising: 2 a second switch positioned in said bypass path; and a terminating resistor connected to a pole of said second 4 switch, said second switch selectively connecting the isolated port 6 of said second hybrid circuit with either said first switch or said terminating resistor.
37. The circuit arrangement of claim 16 further comprising: 2 a second switch positioned in said bypass path; and a terminating resistor connected to a pole of said second 4 switch, said second switch selectively connecting the isolated port 6 of said second hybrid circuit with either said first switch or said terminating resistor.
38. The circuit arrangement of claim 15 further comprising: 2 a first shunt switch positioned between said first power amplifier and said second hybrid circuit; and WO 00/18005 PCT/US99/21758 -22 4 a second shunt switch positioned between said second power amplifier and said second hybrid circuit; 6 said first and second shunt switches being used to shunt the output of said first and second power amplifiers, respectively, 8 when using said bypass path.
39. The circuit arrangement of claim 16 further comprising: 2 a first shunt switch positioned between said first power amplifier and said second hybrid circuit; and 4 a second shunt switch positioned between said second power amplifier and said second hybrid circuit; 6 said first and second shunt switches being used to shunt the output of said first and second power amplifiers, respectively, 8 when using said bypass path.
40. A method for amplifying a signal in a circuit having a 2 driver amplifier, an amplifier path comprising a first switch, a band-pass filter, a first power amplifier, a second power amplifier, 4 a first hybrid circuit and a second hybrid circuit, and a bypass path connecting an isolated port of the second hybrid circuit with the 6 first switch, said method comprising: (A) producing a driver signal from the driver amplifier; 8 (B) selectively switching the driver signal between the amplifier path and the bypass path using the first switch, 10 wherein when the driver signal is switched in said switching step to the amplifier path, said method further 12 comprises: (a) band-pass filtering the driver signal by the 14 band- pass filter to produce a filtered signal; (b) splitting the filtered signal in the first hybrid 16 circuit into an in-phase signal and a quadrature signal; WO 00/18005 PCT/US99/21758 23 (c) amplifying the in-phase signal by the first 18 power amplifier to produce an amplified in-phase signal; (d) amplifying the quadrature signal by the 20 second power amplifier to produce an amplified quadrature signal; 22 (e) inverting the amplified in-phase signal in the second hybrid circuit to produce an inverted signal; and 24 (f) summing the inverted signal and the amplified quadrature signal in the second hybrid circuit to 26 produce a summed signal, and wherein when the driver signal is switched in said 28 switching step to the bypass path, said method further comprises: 30 (a) turning off the first power amplifier and the second power amplifier; 32 (b) transmitting the driver signal to the isolated port of the second hybrid circuit; 34 (c) splitting the driver signal into an in-phase signal and a quadrature signal in the second hybrid circuit; 36 (d) reflecting the in-phase signal off of the first amplifier signal; 38 (e) reflecting the quadrature signal off of the second power amplifier; 40 (f) inverting the reflected in-phase signal in the second hybrid circuit to produce an inverted signal; 42 (g) summing the inverted signal and the quadrature signal in the second hybrid circuit to produce a 44 summed signal; and (h) outputting the summed signal to an output 46 port. WO 00/18005 PCT/US99/21758 24
41. A method for amplifying a signal in a circuit having a 2 driver amplifier, an amplifier path comprising a first switch, a band-pass filter, a first power amplifier, a second power amplifier, 4 a first hybrid circuit and a second hybrid circuit, and a bypass path connecting an isolated port of the second hybrid circuit with the 6 first switch, said method comprising: (A) producing a driver signal from the driver amplifier; 8 (B) selectively switching the driver signal between the amplifier path and the bypass path using the first switch, 10 wherein when the driver signal is switched in said switching step to the amplifier path, said method further 12 comprises: (a) band-pass filtering the driver signal by the 14 band-pass filter to produce a filtered signal; (b) splitting the filtered signal in the first hybrid 16 circuit into an in-phase signal and a quadrature signal; (c) amplifying the in-phase signal by the first 18 power amplifier to produce an amplified in-phase signal; (d) amplifying the quadrature signal by the 20 second power amplifier to produce an amplified quadrature signal; 22 (e) inverting the amplified quadrature signal in the second hybrid circuit to produce an inverted signal; 24 and (f) summing the inverted signal and the 26 amplified in-phase signal in the second hybrid circuit to produce a summed signal, 28 and wherein when the driver signal is switched in said switching step to the bypass path, said method further comprises: 30 (a) turning off the first power amplifier and the second power amplifier; WO 00/18005 PCT/US99/21758 25 32 (b) transmitting the driver signal to the isolated port of the second hybrid circuit; 34 (c) splitting the driver signal into an in-phase signal and a quadrature signal in the second hybrid circuit; 36 (d) reflecting the in-phase signal off of the first amplifier signal; 38 (e) reflecting the quadrature signal off of the second power amplifier; 40 (f) inverting the reflected quadrature signal in the second hybrid circuit to produce an inverted signal; 42 (g) summing the inverted signal and the in phase in the second hybrid circuit to produce a summed signal; 44 and (h) outputting the summed signal to an output 46 port.
42. The method for amplifying a signal of claim 25 wherein 2 the driver signal is a radio-frequency analog signal.
43. The method for amplifying a signal of claim 26 wherein 2 the driver signal is a radio-frequency analog signal.
44. The method of claim 25 wherein the circuit further 2 comprises a second switch positioned in the bypass path, said method further comprising: 4 selectively switching the second switch between connecting the isolated port of the second hybrid circuit to a terminating 6 resistor and connecting the isolated port of the second hybrid circuit to the first switch. WO 00/18005 PCT/US99/21758 -26
45. The method of claim 26 wherein the circuit further 2 comprises a second switch positioned in the bypass path, said method further comprising: 4 selectively switching the second switch between connecting the isolated port of the second hybrid circuit to a terminating 6 resistor and connecting the isolated port of the second hybrid circuit to the first switch.
46. A mobile communication unit having a power supply, a 2 digital processor, a receiving chain, a transmitting chain, a duplexer, an antenna, and user interfacing means, said mobile 4 communication unit comprising: a power amplifier circuit arrangement in said transmitting 6 chain, said power amplifier circuit comprising: a driver amplifier for transmitting an analog signal; 8 a first switch for selectively switching the analog signal between a bypass path and an amplifier path, said amplifier path 10 comprising: a band-pass filter for filtering the analog signal and 12 for producing a filtered signal; a power amplifier for receiving the filtered signal 14 and for producing an amplified signal; a first hybrid circuit for splitting the amplified signal 16 into an in-phase signal and a quadrature signal; and a second hybrid circuit for inverting the in-phase 18 signal to produce an inverted signal and for summing the inverted signal and the quadrature signal to produce a summed 20 signal, WO 00/18005 PCT/US99/21758 27 said bypass path connecting an output of said driver 22 amplifier with an isolated port of said second hybrid circuit when said first switch switches the analog signal to said bypass path, 24 whereby the analog signal transmitted from said driver amplifier will reflect off of said power amplifier and be routed to an output 26 port.
47. The mobile communication unit of claim 31, wherein said 2 power amplifier circuit arrangement further comprises: a second switch positioned in said bypass path; and 4 a terminating resistor connected to a pole of said second switch, 6 said second switch selectively connecting the isolated port of said second hybrid circuit with either said first switch or said 8 terminating resistor.
48. The mobile communication unit of claim 31, wherein said 2 first switch switches the analog signal to said bypass path when said power amplifier is turned off.
49. A mobile communication unit having a power supply, a 2 digital processor, a receiving chain, a transmitting chain, a duplexer, an antenna, and user interfacing means, said mobile 4 communication unit comprising: a power amplifier circuit arrangement in said transmitting 6 chain, said power amplifier circuit arrangement comprising: a driver amplifier for transmitting an analog signal; 8 a first switch for switching the analog signal between a bypass path and an amplifier path, said amplifier path 10 comprising: a band pass filter which filters the analog signal to 12 produce a filtered signal; WO 00/18005 PCT/US99/21758 28 a first hybrid circuit for splitting the filtered signal 14 into an in-phase signal and a quadrature signal; a first power amplifier for amplifying the in-phase 16 signal to produce a first amplified signal; a second power amplifier for amplifying the 18 quadrature signal to produce a second amplified signal; and a second hybrid circuit for inverting the first 20 amplified signal to produce an inverted signal and for summing the inverted signal and the second amplified signal, 22 said bypass path connecting an output of said driver amplifier and an isolated port of said second hybrid circuit when 24 said first switch switches the analog signal to said bypass path.
50. The mobile communication unit of claim 34, wherein said 2 power amplifier circuit arrangement further comprises: a second switch positioned in said bypass path; and 4 a terminating resistor connected to a pole of said second switch; 6 said second switch selectively connecting the isolated port of said second hybrid circuit with either said first switch or said 8 terminating resistor.
51. The mobile communication unit of claim 34, wherein said 2 power amplifier circuit arrangement further comprises: a first shunt switch positioned between said first power 4 amplifier and said second hybrid; and a second shunt switch positioned between said second 6 power amplifier and said second hybrid circuit; said first and second shunt switches being used to shunt 8 the output of said first and second power amplifiers, respectively, when using said bypass path.
AU61549/99A 1998-09-22 1999-09-22 High efficiency switched gain power amplifier Ceased AU772636B2 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US09/158,456 US6060949A (en) 1998-09-22 1998-09-22 High efficiency switched gain power amplifier
US09/158456 1998-09-22
US09/248,048 US6208202B1 (en) 1998-09-22 1999-02-10 High efficiency switched gain power amplifier
US09/248048 1999-02-10
PCT/US1999/021758 WO2000018005A1 (en) 1998-09-22 1999-09-22 High efficiency switched gain power amplifier

Publications (2)

Publication Number Publication Date
AU6154999A true AU6154999A (en) 2000-04-10
AU772636B2 AU772636B2 (en) 2004-05-06

Family

ID=26855042

Family Applications (2)

Application Number Title Priority Date Filing Date
AU61549/99A Ceased AU772636B2 (en) 1998-09-22 1999-09-22 High efficiency switched gain power amplifier
AU61548/99A Abandoned AU6154899A (en) 1998-09-22 1999-09-22 High efficiency switched gain power amplifier

Family Applications After (1)

Application Number Title Priority Date Filing Date
AU61548/99A Abandoned AU6154899A (en) 1998-09-22 1999-09-22 High efficiency switched gain power amplifier

Country Status (6)

Country Link
EP (1) EP1116325A1 (en)
JP (1) JP2002525951A (en)
CN (1) CN1326614A (en)
AU (2) AU772636B2 (en)
CA (1) CA2345089A1 (en)
WO (2) WO2000018004A1 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6806768B2 (en) * 2001-10-31 2004-10-19 Qualcomm Incorporated Balanced power amplifier with a bypass structure
US7902925B2 (en) * 2005-08-02 2011-03-08 Qualcomm, Incorporated Amplifier with active post-distortion linearization
JP5206689B2 (en) * 2007-12-17 2013-06-12 パナソニック株式会社 Amplification circuit with bypass circuit and electronic device using the same
JP2011004556A (en) * 2009-06-22 2011-01-06 Mitsubishi Electric Corp Power supply device for vehicle
CN104158505A (en) * 2013-05-14 2014-11-19 中兴通讯股份有限公司 Radio frequency power amplification circuit, control method and terminal
US9281976B2 (en) 2014-02-04 2016-03-08 Texas Instruments Incorporated Transmitter and method of transmitting
CN104852749B (en) * 2014-02-19 2018-01-16 华为终端（东莞）有限公司 Radio circuit and terminal device
CN104485894A (en) * 2014-11-12 2015-04-01 广州中大微电子有限公司 Common-mode level shift treatment circuit and method for operational amplifier
CN106330121A (en) * 2015-07-02 2017-01-11 株式会社村田制作所 Amplification circuit
CN105353295A (en) * 2015-12-01 2016-02-24 无锡比迅科技有限公司 Operation amplifier gain measurement circuit
CN110708040A (en) * 2019-10-14 2020-01-17 中国科学院微电子研究所 Matched filtering equipment
CN114244378B (en) * 2021-12-13 2023-05-16 遨海科技有限公司 VDES transmitter capable of dynamically outputting power

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3857106A (en) * 1970-09-04 1974-12-24 Bell Telephone Labor Inc Amplifier with n-port signal excitation
US4010426A (en) * 1975-11-12 1977-03-01 The United States Of America As Represented By The Secretary Of The Air Force Rf power amplifier parallel redundant system
GB8517180D0 (en) * 1985-07-06 1985-08-14 W & G Instr Ltd High frequency switched attenuator
US5093667A (en) * 1989-10-16 1992-03-03 Itt Corporation T/R module with error correction
EP0463232B1 (en) * 1990-06-28 1995-08-30 Siemens Aktiengesellschaft Pulse power amplifier
JPH04129309A (en) * 1990-09-19 1992-04-30 Matsushita Electric Ind Co Ltd Amplifier circuit
JPH07115331A (en) * 1993-10-19 1995-05-02 Mitsubishi Electric Corp Amplifying device
JPH09148852A (en) * 1995-11-24 1997-06-06 Matsushita Electric Ind Co Ltd Transmission output variable device
US5974041A (en) * 1995-12-27 1999-10-26 Qualcomm Incorporated Efficient parallel-stage power amplifier
JPH09232815A (en) * 1996-02-23 1997-09-05 Kokusai Electric Co Ltd Variable attenuator for high frequency
US5973557A (en) * 1996-10-18 1999-10-26 Matsushita Electric Industrial Co., Ltd. High efficiency linear power amplifier of plural frequency bands and high efficiency power amplifier
JP2000078035A (en) * 1998-09-01 2000-03-14 Matsushita Electric Ind Co Ltd Transmission circuit and its method

Also Published As

Publication number Publication date
WO2000018004A1 (en) 2000-03-30
JP2002525951A (en) 2002-08-13
AU772636B2 (en) 2004-05-06
CN1326614A (en) 2001-12-12
EP1116325A1 (en) 2001-07-18
WO2000018005A1 (en) 2000-03-30
CA2345089A1 (en) 2000-03-30
AU6154899A (en) 2000-04-10

Similar Documents

Publication Publication Date Title
US6060949A (en) High efficiency switched gain power amplifier
KR100560335B1 (en) Efficient parallel-stage power amplifier
KR100430323B1 (en) Efficient parallel stage power amplifier
EP0829970B1 (en) Dual mode transceiver for TDMA and FDD modes
AU772636B2 (en) High efficiency switched gain power amplifier
US8489033B1 (en) Enhanced wideband transceiver
JP3816356B2 (en) Wireless transmitter
KR20060025150A (en) Shared functional block multi-mode multi-band communication transceivers
WO2000060758A1 (en) Radio device and transmitting/receiving method
KR100257504B1 (en) Periodic beacon signal generator for multi sectorized cell
JP2000013246A (en) Transmitter equipped with plural modulation systems
KR100222798B1 (en) Data transmitting and receiving device using order wore in a wireless communication network
JPH07336268A (en) Dual mode radio equipment
JPH05335975A (en) Radio transmitter
KR20020014260A (en) Mobile terminal unit of cdma mobile communication system using tdd mode
KR20010104076A (en) Transeiver device with pager in cdma mobile communication phone
MXPA99005263A (en) Efficient parallel-stage power amplifier
JP2002135136A (en) Mobile communications equipment

Legal Events

Date Code Title Description
FGA Letters patent sealed or granted (standard patent)