AU615152B1 - Automatic self-frequency synchronizer of display device - Google Patents

Automatic self-frequency synchronizer of display device Download PDF

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Publication number
AU615152B1
AU615152B1 AU68563/90A AU6856390A AU615152B1 AU 615152 B1 AU615152 B1 AU 615152B1 AU 68563/90 A AU68563/90 A AU 68563/90A AU 6856390 A AU6856390 A AU 6856390A AU 615152 B1 AU615152 B1 AU 615152B1
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AU
Australia
Prior art keywords
frequency
signal
voltage
output
resistors
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU68563/90A
Inventor
Young Kwan Yoo
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/12—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
    • H04N5/126—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising whereby the synchronisation signal indirectly commands a frequency generator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/101—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
    • H03L7/102—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop the additional signal being directly applied to the controlled loop oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
    • H03L7/189—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop comprising a D/A converter for generating a coarse tuning voltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronizing For Television (AREA)
  • Controls And Circuits For Display Device (AREA)

Description

AUSTRALI A PATENTS ACT COMPLETE SPECIFICATION 5 1
ORIGINAL
(FOR OFFICE USE) SClass Int Class Application Number: Lodged: Complete Specification Lodged: Accepted: Published: ",Priority: Related Art: 4 0 Name of Applicant(s): .SAMSUNG ELECTRONICS CO. LTD.
Address of Applicant(s): 41.6, Maetan-dona, Kwonsun-u, Suweon-city, o r e a Kyugk.-d SActual inventor(s) YOUNG KWAN YOO I Address for Service: PATENT ATTORNEY SERVICES 26 Ellingworth Parade, Box Hill, Victoria 3128 Complete specification for the invention entitled: AUTOMATIC SELF-FREQUENCY SYNCHRONIZER OF DISPLAY DEVICE The following statement is a full description of this invention, including the best method of performing it known to ii a -J AUTOMATIC SRLF-FREQUENCY SYNCHIRONIZER OF DISPLAY DEVICE BACKGROUND OF THE INVENTION The present invention relates to cathode ray tube (CaT) display devices and more particularly to an automatic self-frequency synchronizer of display devices, which automatically synchronizes a 0 ~self-oscillating fr'Aquency with a constant frequency signal applied to 0o00 the CRT! display device.
o 00 o o ~ccording to the bigh-resolution trend of computer aided design(CAD) 000 and dosk top publiction(DTP) systems which employ the display devices, the hardware manufacturinig companies have different video signals, respectively. Thus, an automatic synchronizer circuit which 0.0 synchronizes a self-oscillating frequency with the frequency signal 0000 applied to the CRT display device has been proposed.
00 0 Fig. 1 shows a conventional automatic frequency synchronizer in which 03 o oo frequency-to-voltage converter FVC provides a do voltage according to .000 0 0 the frequency of ai external input signal. This dc voltage is applied0 0 00to each noninverting W+ terminal of four comparators COMI to CON4 In a 0 0 frequency bund selecting part 200, while reference voltages fixed by voltage dividing resistors RI to R5 are applied to each inverting Hterminal of the four comparators 0011 to 0014. Then, the comparator's COI to 0014 sequentially provide a high-level signal according to the do voltage outputted from the frequency-to-voltage converter FVC.
-2 In other words, the frequency-to-voltage converter FVC provides a higher voltage as the frequency applied from the extornal input signal Increases, and thus the comparators COMI to CON composed of the frequency band selecting part 200 sequentially outputs high-level signals, starting from the first comparator CONi.
Then, four switches 811 to 814 in a switching Part 300 are sequentially turned on by the high-level outputs of the comparators COMI to CON4 in the frequency band selecting part 200 to connect resistors R6 to R9 which are used to determine the frequency value of a osvdiator 0 0000 OSC to a resistor RIO. Thus, the frequency of the oscillator OSC is determined by the time constant according to various coabinatlons of 0 .000resistors R8 to RIO and a capacitor C1, such as the combination of resistors RIO, R9 and capacitor Cl, resistors RIO,R9 and R8 and capacitor resistors RlO,R9,RB and R7 and capacitor C1,, and resistors 0RIO, R9. R8, R7 and RG and capacitor Cl. But, suci, this automatic frequency synchronizer has a drawback to be applicable only for the casL.
of standardized compute-r signals.
That is, the oscillator OSC has no self-oscillating frequency, except the frequencies determined by the combination of the resistors RO 0 0to R10 and th6 capacitor Cl. Accordiagly, oven though tvq display I device corresponds to a multifrequency mode inenitor, its application is possible only in extremely limited range of computers, Moreov'er, in the case of the recent ultrahigh resolution monitors, the systems 'have completely different timing charts, respectively, according to 3manufacturing companies.
SUMMARY OF THE INVENTION It is anl object of the present invention to provide an automatic self-frequency synchronizer which generate& a frequency signal synchronized with any frequency of the external input signal by comparing the self-frequency with the input frequency and by controlling V 'a;'the 08C according to the coamared resultant.
According to the present invention, there is provided an automatic a ~Self-frequency synchronizer of a display device including ai olo~ed phase locked loop composed of a phase comparator PC, a low pass filter, a voltage controlled oscillator, and a counter, comprising :a comparing isans connected between the low Pais filter and the voltage controlled oscillator for comparing the de voltuage of the low pass filter with reference voltages a microcomputer for producing. a stored digital data according to .the output of the comparing means and a 'a digital-to-analog converter for converting the digital data provided from the microcomputer to an analog signal to control the voltage *acontrolled oscillator. 1 BRIEF DESCRIPTION OF DRAWINGS These and other obJects, features, and advantages of the present invention will hecome sore apparent from the following desoription for ,4I~j.
-4 the preferred embodiiwents taken drawings, in which.
Fig.1 is a circuit diagram synchironizer Fig.2 a control circuit synchronizer of display devices and in conJunction with the accompanying of a conventional automatic frequency of is an automatic self-frequency according to the present invention; 4 0 o 4 o C C 440 0 o 00 o 00 4 00 0 0 344 4444 4 04 1 44 0 00 '~00O4 o 0 44 o 4 0.3 0 4 Fig.3 is an waveform diagram of major parts of an automatic self-frequency synchronizer according to the present invention.
DETAILED DESCRIPTION OlF THE PREFERRED ErNhDDIMENTS The present invention will now be described in more detail with reference to the accompanying drawings.
iFig.2 Rthows an automatic self-frequency synchronizer for display devices according to the present invention, which comprises a phase locked loop PLL circuit 400, a comparing circuit 500, a microcomputer MC, and a digital-to-analog converter DAC. The phase looked loop PLL circuit 400 ise the same as the conventional phass locked loop circuit.
To explain in detail, in the phase locked loop PLL circuit 400, the phases of two frequency signals are compared with each other by a phase comparator PC connected to a low pass filter I.PF and the output ot the phase comparator PC is converted to a do voltage by the low pass filter
LPF.
Subsequently, the output of the low pass filter is applied to a voltage controlled oscillator VCO which provides a frequency signal deterined by the tine constant according to the combination of resistors R14 to R16i and a capacitor C2, and the output of the voltage controlled oscillator VCO is 1/N times counted by a divide-by-N counter C to be fed back to the phase comparator PC. Here, N is determined on the basis of the desired frequency of the voltage controlled oscillator
VCO.
This phhse locked loop PLL circuit 400 consisting of the phase coiparator PC, the low pass filter LPFI the voltage controlled *0 oscillator VCO and the counter C can be constructed by using a sin .e integrated chip MC1404BE made by MOTOROLA.
In the comparing circuit 500, the output of the low pass filter LPF is applied to each noninverting term~inal of two comparator CON and COMB, while a reference voltag~e YREF divided by three voltage-dividing resistors R11 to R13 is applied to each inverting H- terminal of the comparators COMB and COW~ In the couparinz circuit 500, when two frequency signals Fl and F2 applied to the phase comparator PC are identical with each other, a first comparator COM6 produces a high-level signal, where~a a second comparator COM6 outputs a low-level signal due to the resulted value from comparison of an output voltage of the low pass filter LPF with theV previously determined reference voltages by the resistors R11 R18, If the frequency signal F1 leads out of phase in the frequency sisnal F2 both comparators COM5 and COMB provide the high level signals in response to the output signal of the low pass filter LPF, whereas if vice versa in the frequency signals F1 Nnd F2 both comparators CON5 and COM6 generate the low level signals. Next, the outputs of the comparators CON5 and CONM are applied to the MC which includes erasable and progranable read only memory(EPROM) to provide the data in accordance with the output of the comparing circuit 600. The output of a microcomputer NC is connected to the digital-to-analog converter DAC which provides an analog signal to a resistor R14 adapted for controlling the oscillating frequency of the voltage controlled o 0 0 oscillator
VCO.
0 In such a structure, when the 'power is turned on, a constant frequency signal from the external input ignal is applied and the microcomputer MC provides an initial digital data storged in the microcomputer MC, recognizing the ON-state of power. Next, the digital Sdata is converted to an analog signal by the digital-to-analog converter DAC and this analog signal is supplied to the resistor R14. Then, the voltage controlled oscillator VCO produces a constant frequency signal 3 a F2' and the frequency of this signal is reduced to 1/N by the counter C.
Subsequently, the phase comparator PC is supplied with the control s al O signal P2 and compares the phase of the external input frequency signal SF1 with that of the frequency signal F2. If both signals 1F and F2 are applied with the sale phase as pulses P1 and P2 in Fig.3, the phase comparator PC provides a signal P7 and this signal P7 is filtered by the low pass filter LPF. The voltage output P8 of the low pass filter LPF: V -7is compared with the reference voltage VIRF In the comparing circuit When the signals Fl and F2 have the same phases, the first comparator COM5 provides a high level signal PS, while the second comparator COMB provides a low level signal P10, by the combination of resistors R11 to R13. Then, the microcomputer MC reads these output signals of the comparing circuit 500 and recognizes that the phaseB of 0 0 frequency signals Fl and F? are identical with each other, Then the microcomputer MC provides continuously the initial data and thus the 0000 voltage controlled oscillator VCO generates the frequency signal Y2' ~0 which is N times the output signal F2 of the counter C.
Next, if the output signal F2 of the counter C of which frequency is 1/N times that of the output signal F2' of the voltage controlled oscillator VO has a lower frequency than the external input signal F1 oo~~ as pulses P3 and H4 in Fig.$, the phase -omparator PC provides an oitlut signal as P11. The output pulse P11 o the phase comparator PC is changed to pulse P12 by the low pass filter LPF and this signal Is applied to the comparing circuit 500, When the phase of F1 Is slower than that of F2, both first and 4 44 second comparatore COM5 and COM6 produces the low level signals as pulses P13 and P14 in Fig 4 3 in accordance with the output voltage of the low pass filter LPF, and comparators COM5 and CONB which is actuated according to pulse P12 supplies a low level, such as pulses P13 and P14 to the microcomputer KC, Then, the microcomputer KC generates a digital -8 data of a lower digit than the initial digital data in response to the lo~w level signals of the comparators CON and~ COMO, so that the digital-to-analog converter DAC supplies the lower voltage than that outputted by" the digital data, to the resistors R14 to RIO and the capacitor C2.
Thus, the voltage controlled oscillator VCO oscillates with frequency signal made by the combination 5- the resistors R14 to RIO and the capacitor C2, than the previous frequency signal. When the 11/N time o 00 00 ultiplied frequency by the oscillated frequency F2' of the voltage 00000controlled oscillator VCO has the lower frequency than that F1 of the 0 0 00 external input signal, the comparing circuit 600 detects this status and -supplies the resultant value to the microcouputer MC. Thus, the uicrocom *ter NC produces its output of which the digital signals is converted to the frequency signal F2' from the voltage controlled Ooscillator VCO, and the lowered frequency signal F2' is 1AM times O 4 reduced by the counter C and is again applied to the phase comparator 00 PC. These steps ure-repeated until the frequency sigals F1 and F2 are identical with each other.
Third, if the frequency signal F2, the output of the counter C, a 00which is 1/N ime multiplied by the frequency signal FZ' from the 0 voltage controlled oscillator VCO according to an initial data value for A- a normal operation of the microcomputer MC, has a lower frequency than the external input frequency signal Yl as pulses P5 and PS in Fig.3, the phase ce' parator PC provides a signal as pulse P15 by comparing phases of pulses F1 and F2 and thin output signal, p15, is changed to pulse pie by the low pass filter LPF. Then, both comparators CQH5 and COMB in the comparating~circuit 500 provide the high level signals as P17 and P18 to *1 the microcomputer MC.
Thus, the microcomputer HC generates a digital data of a higher digit than that of the previous initial data to be outputted to the digital-to-analog converter DAC, according to the high level signals of the first and second comparators COM5 and COMO. Then, the digital -to-analog converter DAC provides a higher voltage than that 00 outputted by the digital data to the rp'sistor R14 so that the voltage 0 0controlled oscillator VCO oscillates with a higher frequincy signal by the combination of the resistors R14 to R16 and the capacitor C2.
When the output signal F2 of the counter C, which is 1/N tutipiled bthe frequency signal F2' from the voltage controlled oscillator VCO, ha oe rqenyta h xera nu rqenysga l h comparators COM5 and COMO detects this status and compares it with each 4 reference voltage to Provide the resulted value to the microcomputer MC, and thus the microcomputer MC increases the frequency of the voltage controlled oscillator VCO by providing a higher digital data, and the increased frequency signal F2' is 1/N times roduced by the counter C and this reduced signal F2, is again applied to the phase cuiparator PC.
These steps are repeated until the frequency signals F1 and F2 are identical with each other. That is, the present inveation comparea the phase of the exte-rnal input frequency signal F1 with that of the L1 internal frequency signal F2 by using the phast' comparator PC and fi ti~rs the autout of the rae comparator PC by using thle low pass filter LPF.
The de output voltage of the low pass filter LPF according to the phase difference is compared with the reference voltage IVREF allotted by the resistors R5 to R7 and the microcomputer MC controls the oscillating frequency of the voltage controlled oscillator VCO in response to the output signals of the comparatore' COMB and COMB. The 0 44 control of tUe microcomputer KC aucording to the output signal of the 0 a Q comparators COMB and COMB is summarized as shown in a table I o 0 0 0 0 0 00 0 00 0 2020 0000 1001 00 01 0 0 0 O 00 0 OOooj 0 0 0 02 0 0 1 0 00 00 0 0 0 1 0 0s CUlB COMB control status of the microcomputer MC low low produce a lover data value than the present output data low high produce the present data high low Not used (inactive) high high produce a higher data value than the present output data As mentioned above, the present inveaition can automatically synchronize the self-frequency signal of the voltage controlled oscillator VCO with any input frequency signal by the control of the ioroonputor HC according to the phase comaricon of saii ipit-anii 58 if-frequency sgas The invention is in no way liaited to the emiodiment described hereinabove. Various modifications of disclosed embodiment as weil as other embodiments of the invention will become apparent to persons skilled in the az~t upon reference to the description of the invention.
It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.
0 0 0 0 o 0 0 0 0 0 0 a

Claims (2)

  1. 2. An automatic self-frequency synchronizer according to claia 1, wherein said comparing leans comprises resistors for dividing a reference voltage and comparators for comparing the output of said low pass filter with the reference voltages divided by said resistors. i. i 9 L- JO 00 13
  2. 3. An automatic self-frequency synchronizer substantially as herein before described with particular reference to figs. 2 aa~d 3 of the drawings. Dated this 27th day of December 1990 A9ATENT ATTORNEY SERVICES Attorneys for SAMSUNG ELECTRONICS CO. LTD. ~0 to 0 0 o 00 0 0 0 0000 0 00 0 0 0 000 0 O 0 0 0 00 0 0~ 0000 0000 0 0 t000 000) 0 *0 0 ii 0 0 0 0 1830 10 0 1 O 0 II 0 9 ~q *9 9~ 4 0
AU68563/90A 1990-04-06 1990-12-28 Automatic self-frequency synchronizer of display device Ceased AU615152B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019900004756A KR910019345A (en) 1990-04-06 1990-04-06 Magnetic frequency automatic synchronization control circuit of display device
KR90-4756 1990-04-06

Publications (1)

Publication Number Publication Date
AU615152B1 true AU615152B1 (en) 1991-09-19

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AU68563/90A Ceased AU615152B1 (en) 1990-04-06 1990-12-28 Automatic self-frequency synchronizer of display device

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JP (1) JPH07325559A (en)
KR (1) KR910019345A (en)
AU (1) AU615152B1 (en)
GB (1) GB2242796B (en)

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GB2279190A (en) * 1993-06-15 1994-12-21 Ibm Synchronisation apparatus
FI98577C (en) * 1995-03-28 1997-07-10 Nokia Mobile Phones Ltd Oscillator center frequency tuning method
DE19547609A1 (en) * 1995-12-20 1997-06-26 Bosch Gmbh Robert Clock synchronization method
GB2330258B (en) * 1997-10-07 2001-06-20 Nec Technologies Phase locked loop circuit
US6229401B1 (en) * 1998-08-07 2001-05-08 Thomson Consumer Electronics Horizontal frequency generation
EP1698056A1 (en) * 2003-12-19 2006-09-06 Philips Intellectual Property & Standards GmbH Method and arrangement for interference compensation in a voltage-controlled frequency generator
KR100564639B1 (en) 2004-11-06 2006-03-28 삼성전자주식회사 A functional blocks for controlling the state of a display and method thereby
FR2946488B1 (en) * 2009-06-03 2012-05-04 St Ericsson Sa FREQUENCY OFFSET CORRECTION
US8698566B2 (en) * 2011-10-04 2014-04-15 Taiwan Semiconductor Manufacturing Company, Ltd. Phase locked loop calibration

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US3567860A (en) * 1968-03-07 1971-03-02 Hewlett Packard Co Television synchronizing system
NL171403C (en) * 1972-06-15 1983-03-16 Philips Nv A circuit for generating a control signal for the grating deflection in a television receiver, as well as a television receiver thereof.
US4272729A (en) * 1979-05-10 1981-06-09 Harris Corporation Automatic pretuning of a voltage controlled oscillator in a frequency synthesizer using successive approximation
JPS5843632A (en) * 1981-09-01 1983-03-14 テクトロニツクス・インコ−ポレイテツド Phase fixing circuit
DE3578493D1 (en) * 1984-10-16 1990-08-02 Philips Nv SYNCHRONIZER CIRCUIT FOR AN OSCILLATOR.
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GB8618140D0 (en) * 1986-07-24 1986-09-03 Microvitec Plc Horizontal deflection stage
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JPH01149512A (en) * 1987-12-04 1989-06-12 Matsushita Electric Ind Co Ltd Automatic frequency control circuit
JPH01158878A (en) * 1987-12-15 1989-06-21 Canon Inc Picture reader
JP2877855B2 (en) * 1989-10-03 1999-04-05 旭化成マイクロシステム株式会社 PLL circuit

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GB2242796B (en) 1993-12-08
GB9100485D0 (en) 1991-02-20
GB2242796A (en) 1991-10-09
JPH07325559A (en) 1995-12-12
KR910019345A (en) 1991-11-30

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