AU614378B2 - A configuring device - Google Patents

Description

614378 COMMONWEALTH OF AUSTRALIA PATENTS ACT 1952-1969 COMPLETE SPECIFICATION FOR THE INVENTION ENTITLED "A CONFIGURING DEVICE" The following statement is a full description of this invention, including the best method of performing it known to us:f A configuration device is a device connected to electrical or electronic equipment of any kind whatsoever and which is used to introduce in it, in a modifiable manner, numerical or assimilated data defining particular operating conditions of that equipment. Such data can for example, be one or more transmission or reception frequencies, for a transmitter or for a receiver, or other characteristics of the signals treated, or yet again parameters for the control of the equipment.

The simplest mode for the realisation of such a configuration device is a strip fitted with movable connectors (straps) whose presence conditions the supply of configuration signals. Its use is awkward and requires a direct manual intervention on the equipment. It is to be avoided in numerous cases. Moreover, the number of distinct values which can be introduced in that manner is relatively low compared to the capacity.

Another simple solution consists in providing switches instead of straps. This only avoids direct manual intervention on the equipment. The other disadvantages still remain.

A more recent solution giving total technical satisfaction consists in providing for configuration registers receiving and displaying configuration signals. But then, one must provide means for the visual display of the content of these registers to an operator having to intervene on the configuration signals. It is also necessary to provide means to modify the contents of the registers. If the equipment in question is equipped with a processor with stored programme and input/output systems, it can supply simply the means of access just mentioned. The registers in question are then, for example, connected to the input/output bus of that processor. If the equipment Sin question is not equipped with its own process but is connected directly to the input/output bus of an external processor, the solution remains the same.

In fact, the invention concerns the case of equipment which does not include such processors or which cannot be used to that end.

An obvious solution would be to add a processor to the equipment, specifically assigned to the configuration device. It has been shown that this solution had some serious disadvantages, not so much because of the cost involved by the solution itself, but rather in the long delay necessary for the design, construction, testing and the implementation of such a configuration device for each new application, and in the use of heavy and costly material (carrying out an emulation, for example).

There is therefore a need for a configuration device which has all the advantages of a device with processor with stored programme but which does not have the disadvantages mentioned.

According to the invention there is provided a configuration device for the reading and modification of the content of configuration registers supplying configuration information of electronic equipment, comprising: a sequencer with memory capable of scanning a succession of status and of supplying in each status a specific status information, a manual control with which an operator supplies control signals intervening in the functioning of the sequencer, in such a way to at least modify the succession of status it scans, an address decoder exploiting an address information contained in at least some of the said information status and supplying signals selecting a configuration register, an incrementer receiving the configuration information supplied by a selected configuration register and, on the command of a status infori i jJ 3t

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~I~t I Smation element, supplying that configuration information, after modifying it to a predetermined value, so that it can be re-entered, as modified, into the configuration register from which it came, Sa display device receiving in particular the configuration information supplied by a selected configuration register and supplying a visual i representation of that information.

i I Such a system is simple. Its essential element is the memory of the i sequencer which contains a programme which is easy to test and to prepare.

Preferably the display device comprises a display and a transcoder converting the signals that are addressed to it for display in signals suiting the display unit.

This allows for the use of the display unit not only to view the configuration signals contained in the configuration registers, but also other information coming from the sequencer especially, such as the identities of the registers whose content is going to be displayed.

It is an advantage that the manual control supplies separately at o least two distinct signals, a selection signal to address successively the various configuration registers, and an incrementation signal for the in- S° cremental modification of the content of the register selected.

f c2' It is also an advantage that the display device comprises at least one group of display units as well as the means allowing for the selection of display units so that one of these displays the identity of a selected register and the other displays the content of that register. The operator thus sees the identities of the configuration registers as he/she repeatedly activa'ces a selection button and modifies the values contained in the S register whose identity is displayed when the incrementation button is activated.

1 In order that the invention may be readily carried into effect, an embodiment thereof will now be described in relation to the drawings, in which: Figure 1 shows a block diagram of an embodiment of the invention; Figure 2 shows a chronogram illustrating the way the configuration device in Figure 1 works.

Referring to Figure 1, the configuration registers REG contain the configuration information of an equipment which is not representative of any type whatsoever and the configuration signals supplied to that equipment by the link 11lcf". These registers are doubled by reading registers 1RLC with the same configuration, so as to allow for the reading and modification and entering of a configuration information at the same time.

The configuration device in Figure 1 comprises moreover a clock OLK, a sequencer SQR, an address and entry decoder DAE, a reading address decoder DAL, reading buffer registers 1RLC, an incrementer INC, a display device DAF comprising a cranscoder TRO and a display IAFF. The unit is controlled with a control device ODE which can be abstracted into two control buttons activating respectively the control contacts "pro" and "inc".

The sequencer SQR is a memory, which can be constituted by a 270256 INTEL. At each pulse of the clock "1hsq1", a reading operation is carried out at an address defined by the signals then present in the address entry "ads". The information contained at this address is supplied on the output "1ssq11 of the memory. It is to be noted that- at least a part of the infor- P mation read returns through the loop "bad" tvowards the address entry "ads", where it is completed by the control signals supplied by the control device ODE, to form the reading address to be used later. Thus, each step of the memory reading forming the sequencer SQ supplies elements of the address of the following reading step. Each reading step corresponds to a status of the sequencer in a succession of status reached by successive reading operations and the control device ODE allows for an intervention in this succession of status scanned by the sequencer, as will be seen in more details later when referring to Figure 2.

A status or the sequencer is thus defined by a memory address, which supplies a group of reading signals obtained in a reading step.

The decoder DAE receives from the sequencer SQEL address signals fladr" and an entry control signal llwrll: it supplies in exchange decoded entry address signals 'lade". Similarly, the decoder DAL receives from the sequencer SQR address signals 11adrll and a reading control signal read: in exchange it supplies decoded reading address signals "adl". The active level of the l"wr"l and read signals is level 0 and signals "adel" and 1ladl"l are supplied by the DAB and DAL decoders when signals "wrr" and "read" are at level 0 respectively. These two separate decoders can be seen as the one and the same configuration register decider supplying to a selected register either a reading signal "adl", or an entry signal 'lade".

The configuration registers REQ are, for example, a unit of identical registers each containing two hexadecimal numbers with four bits. The output signals of these registers constitute, as we have seen, the configuration information which is supplied on the link "l1cf"l. The register among these which is selected by a decoded entry address signal 'lade" receives and memorizes the incremented configuration information which is then supfplied to the incrementer INC on the link "Ibnc".

01) Moreover, the configuration information is also communicated to the reading buffer registers iRLO, forming a unit similar to that of the registers unit REG, both by their number and by the addresses which identify them. The registers RIC thus copy in some way the information contained in the registers REG. The register BLO designated by the decoded reading address signals "ladl"l supplies on its output l"bnl"l the information it contains in the direction of the incrementer INC and of the transcoder TEC.

During that time, its output is blocked; it is not then sensitive to the information coming from the register REG. Moreover, one can check by re- 6 ferring to Figure 2, that the RLC registers outputs are blocked when an entry operation is carried out in the REG register. The transcoder TRC receives not only the configuration information supplied on its output "bnl" by a selected reading buffer register, but also address and sequence signals supplied on the sequencer output "ssq". It converts these signals into a code directly usable by a display on its itput "caf". The display AFF will comprise several display elements "affl" to "aff4" and one of these, each time, designated by signals from the sequencer SQR output "ssq" receives, memorizes and displays the coded signals supplied by the transcoder TRC on its output "caf".

Referring to Figure 2, whilst still referring to Figure 1, to give an example of the operating of the sequencer overall.

Figure 2 represents an operating chronogram of the configuration device in Figure 1.

The lines in this diagram represent the individual signals produced by the sequencer SQR on its output "ssq". The columns define, from left to right, what becomes of these individual signals during that time, each column corresponding to a status of the sequencer SQR. At the top of each column we have indicated, from top to bottom, the designation of the corresponding status sequencer, under the form of the hexadecimal representation of the binary signals indicated in the column.

In each status of the sequencer, the status information supplied on its output "ssq" thus comprises, as illustrated by line 2: -1 a signal STL2 not used in the example described, a signal readd intended to activate the output of the incrementer INC, address signals S5, S4, S3, 32, Sl, SO collectively forming the address "adr" in Figure 1, A flash signal intended to activate the incrementer INC and to wipe out i the display,

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signals AAl and AAO which in fact constitute a complement to the address, especially for the display, a signal STL1 used to distinguish two sequencer status in other respect Iidentical, the signal wr controlling the entry into the configuration registers

REG,

a signal "iwr" controlling the memorization and the display on display AFF of the information transcoded by the transcoder TRC, the signal read controlling the reading, in one of the reading regisi ters RLC, of configuration information to be displayed and/or modified.

The operating example proposed in Figure 2 consists in displaying the identity of a configuration register and the content of that configuration S. register and, if the contact"inc" of the control device CDE is closed, in 1 incrementing one of the numbers in the content displayed. The operation is repeated, until the contact "pro" of the control device CDE is in its turn S, operated, which provokes the passage to a following operation cycle, also illustrated in Figure 2, almost identical, for the eventual incrementation of the other number in the content of the selected configuration register.

o An anterior operating cycle was carried out, where a starting position S, was initiated any appropriate means (forcing all elements of the device into a predetermined starting position, for example). An address is thus supplied on the sequencer SQR entry "ads" and the sequencer supplies the 8 IX_ status information illustrated in the first left hand column in Figure 2 and translated by the hexadecimal expression 21B4.

This status information comprises an address "adr" formed by signals SO to 35, supplying the binary value 110000, which will remain stable during the operation cycle illustrated by the first half of Figure 2. It designates a particular configuration register, which we shall call IBS for clarity, this reference being represented at the top of Figure 2.

Signals AAl and AAO have a value of 1. We shall return to their role during the description of the next status of the sequencer. The "read" and "wr" signals are on level 1 whilst the other signals are on level 0.

The "read" signal on level 0 validates the decoder DAL. The latter in this example, exploits the signals Sl to S4 and selects a reading register from up to 16 registers RLC. This register receives a signal "adl" and supplies the configuration information it contains on the output "bnl".

The transcoder TRC receives among others, the signals S4 to SO, flash, and AA1, AA0. Here also it is a memory, similar to the memory in the sequencer. In exchange for these signals, it supplies a coded combination on its output "caf" ready to control a display. Due to the fact that Ssignals AA1 and AAO are on level 1, the transcoder TRC supplies a coded combination representing the first of the two characters of a designation corresponding to the address defined by signals S4/SO. This designation can thut; be defined arbitrarily, for example, obey mnemonic considerations.

o All the status signals which we have just described, except for the S"readd" and S5 signals are returned by the loop "bad" to the address entry "ads" of the sequencer SQR. They are completed by two signals coming from the control device CDE and characterizing the position of the "pro" and "inc" contacts of the two control buttons. In the following, it will be supposed firstly, that the "pro" and "inc" signals are taking the place of the "readd" and S5 signals, and secondly, that the binary values of these i signals are 1 and 0 respectively, the same as those of the "readd" and signals.

The 21B4 address is thus supplied on the "ads" entry. It is read at the following clock pulse "hsq" and the status information "read" in this second reading step is represented in the second column in Figure 2. It has an hexadecimal value of 21B6. It only differs from the preceding one by the level of the "iwr" signal which becomes 1.

The transition of the signal "iwr" from 0 to 1 leads to the memorization of the information which is always present on the link "caf", in the S 10 display AFF, for the benefit of one of the display elements "affl" to "aff4", according to the value of the signals AA1, AA0 which are also transmitted to it. Thus, for example, the fourth display element "aff4" displays the first character of the designation corresponding to register

IBS.

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The status information 21B6, taking into account the control signals indicated above, becomes address 21B6, which is read in the sequencer SQR at the next clock pulse. The new status information obtained has a value of 21A4. The signal "iwr" comes back to level 0, whilst the signal AAO passes to level 0.

In this new step of the sequencer, the information transmitted to the transcoder TTG is modified (AAO=0). As a result, the transcoder TRC supplies the second character of the designation of the configuration register indicated by address "adr".

The status information 21A4 becomes address 21A4 and the next sequencer step supplies a new status information 21A6. In a manner similar to the one described for the sequencer step 21B6, the third display element "aff3" receives thus the second character of the designation of the configuration register selected.

At the next sequencer step, with a 21A6 address, the status information is 2194. The signals AAl and AAO supplied to the transcoder C have i 1 :i i ii ii ii 1 i;: P3 j j i.

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Sa value of 01 and the latter then supplies a character which is derived from the configuration information present on the link "bnl". It is to be noted that this information comprises two numbers with four bits. The signal SO designates the number out of these two numbers which is to be displayed.

At the next sequencer step, with a 2194 address, supplying status information 2196, the character supplied by the transcoder TRC on the link j "caf" is displayed by the second display element "aff2".

At the next sequencer step, with a 2196 address, supplying status in- S 10 formation 2184, the signals AA1/AA0 become 00. The transcoder TRC supplies i a character to be displayed derived from the second number coming from the i configuration register selected.

At the next sequencer step, with a 2184 address, supplying status information 2186, the character supplied by the transcoder TRC is displayed i by the first display element "affl".

At that time, the display is complete. The operator can see on the display the designation of a configuration register and the content of that register.

At the next sequencer step, with a 2186 address, supplying status in- S 20 formation 218E, the signal STL1 passes to level 1. Nothing happens. The Ssequencer passes then to the next step, with a 218E address and supplying i ,status information 3134. What follows will be described further on. It is appropriate to note that the influence of the control signal "pro" provoked the sequencer to jump a few steps. "We shall now suppose that at the be- S.ginning of the cycle, or at any time before arriving at the step of address 2186, the operator supplies the signal "inc" and not signal "pro". If that were to happen at the beginning of the cycle, the addresses scanned are 11B4, 11B6, 11A4, 11A6, 1194, 1196, 1184, 1186. The content of these addresses is the same as that of their opposite numbers whose first number is 2 instead of 1 shown on Figure 2. The passage from one address sequence to 11 i': another can therefore occur anywhere. However, at the end of the display procedure, address 1186, as distinct from address 2186, supplies this time status information 2106.

The flash signal passes to level 1. It blocks the operation of the transcoder TRC and provokes the operation of the incrementer INC which calculates a value comprising one of the two numbers of the information which is applied to it by the link "bnl", without modification, and the other number, increased by the increment intended, for example, by one unit.

At the next sequencer step, with a 11C6 address, supplying status information 21C7, the signal "read" passes also to level 1, the reading register selected then stops supplying the reading information on link "bnl".

At the next sequencer step, with a 11C7 address, supplying status informatin 01C3, the signal "readd" and the signal "wr" pass to level 0.

The signal "readd" applied to incrementer INC, validates the output of the latter; the incrementer INC thus supplies on link "bnc", in direction of the register REG, the configuration information incremented as indicated above. The signal applied to the entry address decoder DAE, is translated by a decoded entry signal "ade" which is applied to one of the configuration registers REG, corresponding to the address "adr" still supplied by the sequencer SQR.

At the nuxt sequencer step, with a 11C3 address, supplying status information 01CF, the signal "wr" returns to level 1 which determines the load, in the configuration register selected at the preceding step, of the information present on the output link "bnc" of the incrementer INC. At Sthe same time, the signal STL1 passes to level 1.

At the next sequencer step, with a 110C address, the status information is 218F. At the next sequencer step, with a 118F address, the status information will be 21B4, which brings us back to the beginning of the operating cycle just described, for a new display of four characters, com- 12 V prising this time the value modified by the incrementation of the content of the configuration register selected.

It is, however, possible to provide for the wait of the end of signal "inc before the return to the beginning of the cycle, by foreseeing that at address 11CF, the status information is 21CF, instead of 218F. The resulting address will be 11CF, so that the sequencer will remain in that unique status, until the control device CDE supplies these "pro" and "inc" signals with a value of 0. The address read will then be 01CF and this latter will contain only status information 218F.

One can also foresee the case when the operator does not push any control button; the "pro" and "inc" signals remaining at level 0. The sequencer can then scan a succession of status, from 01B4 to 0184, similar to the two status succession described earlier when the first number was 2 and 1 respectively, for the complete display, following which the return to the beginning of the cycle can be obtained by a direct jump to 218F which leads to 21B4 as we have seen. The case when both buttons are pushed together and the "pro" and "inc" signals are both on level 1 can be treated in the same manner.

The second half of figure 2, describing status 3134 to 310E is in all S 20 aspects similar to the first one we have just described except for signal SO which has a value of 0 instead of 1 and signal S5, symetrically which has a value of 1 instead of 0. The operation is the same but it concerns the other number of information contained in the same configuration register.

At the end of this second procedure, the sequencer can pass into another status, for the reading and eventual modification of another configuration register. The same system moreover also allows for the reading of information entered into registers treated like configuration registers.

It can be seen that the definition of the data to be entered into the memory of the sequencer, in application of the preceding expose, is a rela- IL I tively simple operation, which can moreover be carried out with the help of general purpose computer.

Moreover, figure 1 also shows, with a broken line, an input connection "inl" on link "bnl". Such a link, with an appropriate interface, would allow the configuration device in this invention to receive information coming from an external calculator. As for link "cnl", it illustrates the fact that the link "bnl" and link "inl" can be connected directly to the registers REG inputs, allowing the registers REG to receive information without the interposition of an incrementer. Of course, the address signals "adr" and the control signals "read", would have to be supplied accordingly, either through the sequencer SQR, or through an external calculator.

It is quite obvious that the preceding descriptions have been given only as an example and are not restrictive and that numerous variations can be considered, which can still be within this invention.

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Claims (4)

1. A register control device for reading and modifying the contents of each of a U plurality of configuration registers, wherein each register contains address informa- tion and alterable configuration information, the register control device including: a sequencer with a sequencer memory, the sequencer producing sequencer output signals including a sequence of address signals containing the address each of the configuration registers to scan the status of the configuration information of the ad- dressed configuration registers, the sequencer being capable of providing configura- tion control signals to alter the contents of each configuration register as it is addressed, a manual control which is capable of supplying sequence control signals to inter- vene in the operation of the sequencer to at least modify the sequence of address signals, the manual control being capable of supplying configuration control signals to alter the configuration information in an addressed configuration register, 15 an address decoder decoding the address signals and addressing the corresponding S configuration register, an incrementer which receives configuration information from an addressed con- figuration register, the incrementer being capable of modifying the configuration in- I' formation in response to a configuration control signal, whereupon the incrementer writes the modified configuration information into the respective configuration regis- ter, and a display device receiving the configuration information supplied by the ad- S, dressed configuration register and providing a visual representation of the configura- tion information.

2. A register control device as claimed in claim i, wherein the display device comprises a display and a transcoder converting received signals to signals suited to the display.

3. A register control device as claimed in claim I or 2, wherein the manual con- trol supplies separately at least two distinct signals, a selection signal to address suc- cessively the various configuration registers, and an incrementation signal for the incremental modification of the content of the selected register. t

4. A register control device as claimed in any one of the preceding claims, wherein the display device comprises at least two groups of display units, as well as means to select display units so that one of the said groups displays the identity of a 1 register selected and the other displays the content of that register. -AT O. V 2 16 A register control devicc, suibstantially as herein described with reference to Figures 1 and 2 of the accompanying drawings. DATED THIS ELEVENTH DAY OF JUNE 1991. ALCATEL. N.V. LI Ii Li Fl >1 ii N 41444 1 4 4444 4 4 It II (444