AU607639B2

AU607639B2 - Apparatus for parallel operation of triport uninterruptable power source devices

Info

Publication number: AU607639B2
Application number: AU42429/89A
Authority: AU
Inventors: Yasuhiro Kawata; Hidehiro Koike; Fukutoshi Tominaga
Original assignee: Nishimu Electronics Industries Co Inc
Current assignee: Nishimu Electronics Industries Co Inc
Priority date: 1988-10-25
Filing date: 1989-10-02
Publication date: 1991-03-07
Anticipated expiration: 2009-10-02
Also published as: GB8922379D0; AU4242989A; FR2638299A1; GB2224895B; DE3935564A1; JPH02119541A; CA1319412C; GB2224895A; JP2849598B2; FR2638299B1

Description

8 7639 COMMONWEALTH OF AUSTRALIA PATENTS ACT 1952 COPEE SEC IFCAflQN NAME ADDRESS OF APPLICANT: C 4 4' Nishimu Electronics Industries Co., Ltd.

1-82, Watanabe-dori 2-chome Chuo-ku, Fuk-uoka-shi Fukuoka-keii Japan NAME(S) OF INTVENTOR(S): Fukutoshi TOM]NAGA Yasuhiro KAWATA Hidehiro KOIKE This documrnmt contains U., an~e~ndmn ts r' ciae unJC Scction '9 and is correct for Spr1i ting.

r ADDRESS FOR SERVICE: DAVIES COLLISON Patent Attorneys 1 Little Collins Street, Melbourne, 3000.

COMPLETE SPECIFICATION FOR THE INVENTION ENTITLED: Apparatus for parallel operation of triport uninterruptable power source devices The following statement is a full description of this invention, including the best method of performing it known to me/us:la BACKGROUND OF THE INVENTION Field of the Invention: This invention relate to an apparatus for the parallel operation of a plurality of triport uninterruptable power t C C e e source devices arranged in parallel connection and adapted S t c z to feed power to a load.

se Description of the Prior Art: l40 The dissemination of computers and microprocessors has been increasing importance to uninterruptable power source devices as operating power sources for such electronic devices. When the power required by a given load is so large as to surpass the capacity of one uninterruptable 15 power source device, it becomes necessary to feed an 0 increased magnitude of power by parallel operation of a plurality of power source devices.

e In most cases, such uninterruptable power source device for parallel operation as mentioned above is generally configured with a conventional uninterruptable power source comprising of a battery-driven inverter device and a commercial power source which are connected in parallel each other, and some additional battery-driven inverter devices connected in parallel to said conventional uninterruptable power source [as reported in the treatise titled "On the 2 Paralleling of UPS systems" by Clement Fontaine at the 1986 International Telecommunications Energy Conference, for example].

The use of such uninterruptable power source divices (hereinafter referred to briefly as "UPS") of prior art as described above entails the following problems.

Firstly, the burdens of load laid on the individual UPS's are desired to be proportionate to the inverter capacities of the USP'c. The control for the proportionate load distribution is not easy to effect. In the conventional UPS's, the output currents depend on the phases of inverter drive pulses and increase in proportion as the phases advance. For the purpose of the proportionation mentioned above, it is necessary to detect the output currents of the inverters in parallel operation and control the phases of the inverter drive pulses in accordance with the inverter capacities and the detected output currents.

The circuit for this control and the method for its operation are highly intricated. Thus, the control cannot be easily carried out with high reliability.

Secondly, the circulating current which occurs between the inverters of the UPS's under parallel operation when a phase difference is produced between the output voltages of the inverters is suppressed only with difficulty. The suppression of the circulating current may be possibly attained by inserting a current limiting element such as i ~C -3a reactor in each of the inverter circuits or by detecting the circulating current and accordingly adjusting the drive timing (phase) of the inverter. In this case, there arises the problem that the number of circuit elements required for the control is increased or the problem that the circuit for the timing adjustment is intricated.

Thirdly, concerning the synchronous operation required for the inverters of the UPS's under parallel operation, 0o while the conventional UPS's are controlled with high ono 10 responsiveness because of their small internal inductance, 0000 ooO they have the problem that a disruption of the synchroni- 0o zation among the plurality of inverters results in a very S0OO large circulating current. To cope with this problem, the synchronization among the inverters must be controlled o 15 very accurately and quickly. The circuit for realizing 0 00 such accurate and quick control of the synchronization o. as mentioned above necessitates advanced design and t o 0000 00,,o0 complicated configuration and suffers from high cost and 0 0 poor reliability.

Fourthly, when any of the UPS's under parallel operation developes a trouble, it must be parallel off as soon as possible. Since the conventional UPS has a small internal inductance as mentioned above, an accidental short circuit may possibly result in an excessive rate of increase in the short-circuit current. The preclusion of such trouble calls for early detection of the undue short-circuit I i 1 1 -4current and quick parallel-off of the UPS in trouble. The circuitry capable of fulfilling this requirement is so complicated as to entail the disadvantage of high cost and poor reliability.

BRIEF SUMMARY OF THE INVENTION According to the present invention there is provided apparatus comprising at least one triport uninterruptable power source device connected, in use, between an AC input power source and a load and being adapted for connection in parallel with other triport uninterruptable power source devices, said at least one triport uninterruptable power source device comprising: c a three-winding transformer having a first, a second and a third winding; an AC input connected to the first winding ofhe transformer through a first inductive component; a S 15 an inverter connected to the second winding of the transformer through a second inductive component; an output terminal connected to the third winding of the transformer through a paralleling switch; an inverter driving means for driving the inverter in synclronization with the 20 AC input; an AC input monitoring circuit for detecting normality or abnormality of the 4 AC input; and a mode controlling means for controlling the switching of the inverter, in 9 accordance with the output of detection from the AC input monitoring circuit, between a standby mode in which no output current is generated by the inverter and an inverter mode in which an output current is generated.

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BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic block diagram illustrating one embodiment of this invention.

Fig. 2 is a block diagram illustrating a specific configuration of one triport

UPS.

Fig. 3 is a block diagram illustrating a specific configuration of an operating mode monitoring circuit.

Fig. 4 is a block diagram illustrating a specific czI; t It~ 4 4 4, .4 4044 4 I 444 4. 4 4, (S 4, 4,4 4444 4, 4.4, 4, 4,4* *444 4,4.

4 9i 44 4 .4

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configuration of a parallel synchronizing signal generating circuit.

Fig. 5 is a block diagram illustrating a specific configuration of a synchronization monitoring circuit.

Fig. 6 is an equivalent circuit diagram to explain the operation when a paralleling power source according to the present invention is switched from the inverter mode to the normal mode.

Fig. 7 is a perspective view illustrating in schematic Fig. 1 is a schematic block diagram illustrating one embodiment of this invention. Though the diagram depicts 4, 115 three triport UPS's arranged in parallel connection, it ought to be apparent that the number of triport UPS's to be parallelly connected can be changed at will.

9 4 The triport UPS's 1 to 3 are mutually connected in a DC input bus 7. The AC input bus 5 is connected to an AC commercial power source 9. The DC input bus 7 is connected to a storage battery 10 (generally a DC power source) and the storage battery 10 is charged from the commercial power source 9 through a charger 12.

The AC output bus 6 is connected to an output terminal through an output breaker 14. The commercial power -7 -/r source 9 is connected to the output terminal 15 through a bypass line 17 and a bypass breaker 18. The three triport UPS's 1 to 3 are mutually connected through a control signal bus 20 and subjected to control of synchronization and control of mode as described specifically hereinafter.

The triport UPS's 1 to 3 illustrated in Fig. 1 have one and the same structure. Fig. 2 is a block diagram illustrating a typical structure thereof.

An iron core 22a of a triport transformer 22 is divided 0 "10 into three sections by two magnetic shunts 22d, 22e. An AC 00 0 o 00 o 00 oot input winding 22b, an inverter input winding 22f, and an 0 output winding 22c are severally formed in these sections.

r*@o The AC input winding 22b is connected to the AC input bus 5 through a line switch 23 and the inverter input winding 22f is connected to the output terminal of an inverter 26 through an inverter switch 24. The output 0:a: o winding 22c is connected to the AC output bus 6 through a0 a paralleling switch oooo o0.. Optionally, the switches 23 to 25 may be configured 0 0 with a pair of thyristors arranged in reverse parallel l connection, for example. To the output side of the transformer 22, a suitable known voltage stabilizer 35 is connected. The input side of the inverter 26 is connected to the DC input bus 7 through a current detector 37.

An AC input synchronizing signal generating circuit 27 generates a trigger pulse (reset signal) synchronized to the commercial power source (particularly to the zero cross point). The synchronized trigger pulse is transferred through an AC-terminal of a changeover switch 28 to an oscillating circuit 29 and used therein to trigger the circuit.

An inverter monitoring circuit 32 compares the rectangular wave from an inverter driver 31 for driving the inverter 26 with the output wave from the inverter 26 in phase and pulse width and, when their difference exceeds the 00 0 o0 ,10 prescribed value, draws a conclusion that the inverter 26 is 0 0 0 oot abnormal, and issues a trouble signal F.

00 0 e 0 The trouble signal is used not only in displaying and/or warning the abnormality of the inverter by way of alarm, opening the inverter switch 24 and/or bringing the operation of the inverter to a stop but also in opening the 06 0 paralleling switch 25 to release the triport UPS in trouble o0 o 0'o oo from the parallel operation.

o o An AC input monitoring circuit 34 monitors the oo00 oooo commercial power source 9 by way of conventional method 0 (based on possible deviation from the standard value of t voltage level, cycle of frequency at zero cross'point, A' or voltage waveform, for example) and, on detection of abnormality, turns the changeover switch 28 to the opposite, i.e. an IN-terminal, illustrated in the diagram.

ne output from the AC input monitoring circuit 34 is simultaneously fed to an operation mode monitoring circuit 7 1 38 and to operation mode monitoring circuits of the other triport UPS's under-parallel operation which are not shown.

The operation mode monitoring circuit 38 is supplied the outputs of detection by the AC input monitoring circuits 34 of the pertinent triport UPS and the other triport UPS's 2 and 3 under parallel operation and, on the basis of the result of the logic operation (which is described hereinafter with referring to Fig. 3) performed on these outputs of the AC input monitoring circuits, issues a mode control 9 6 signal and parallel-off signal.

0 a A mode controlling circuit 39, on reception of the mode oa control signal, controls a phase shifter 30 and, when the a a commercial power source or the AC input is normal, delays the phase of the inverter drive rectangular wave (the output from the oscillating circuit 29) so as to effect substantial c nullification of the input current to the inverter 26 (to be to detected by the current detector 37) and while, when the AC input is abnormal, advances the phase of the inverter drive 0 0o rectangular wave so as to equalize it to the phase of the AC input in normal state and, at the same time, opens the line switch 23 to release the commercial power source from the transformer 22.

A parallel synchronizing signal generating circuit 41 is supplied the rectangular wave outputs by the oscillating circuits 29 of the pertinent triport UPS and other triport UPS's 2 and 3 under parallel operation and, on the basis of 4 4/ the result of the logic operation (which is described in detail hereinafter with referring to Fig. 4) performed on the rectangular wave output signals, feeds a synchronizing trigger pulse to the IN terminal of the changeover switch 28.

Fig. 3 is a block diagram illustrating a specific configuration of the operation mode monitoring circuit 38.

The detection output signal from the AC input monitort ing circuit 34 and the detection output signals from the AC 10 input monitoring circuits of the other triport UPS's 2 and 3 *et oor Of 4 under parallel operation are fed as paired to AND circuits 51 to 53, respectively.

In the embodiment under discussion, therefore, the output is produced by any of the AND circuits 51 to 53 when the detection output signals from and two of the three triport UPS's 1, 2 and 3 are both namely when the AC inputs in any two triport UPS's are judged as normal (generally by the rule of decision by majority) or when the 444444 AC inputs in the prescribed number sets of triport UPS's among the total sets are judged as normal.

Conversely, the outputs of the AND circuits 51 to 53 are invariably when the detection output signals from any two of the three triport UPS's 1, 2 and 3 are both "O's" (generally by the rule of decision by majority) or when the AC inputs in the prescribed number sets of triport UPS's among the total sets are judged as abnormal.

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The outputs from the AND circuits 51 to 53 are applied to the mode control circuit 39 through an OR circuit 54.

The resultant coincident operation mode is used as an operation mode for all of the triport UPS's 1, 2 and 3 in the parallel operation system.

The detection output signal from the AC input monitoring circuit 34 of the pertinent triport UPS 1 is combined with the detection output signals from the AC input monitor- "x ing circuits of the other triport UPS's 2 and 3. The combined signals are fed to two-input exclusive OR circuits 55 and 56.

The exclusive OR circuits 55 and 56 produce no output when the detection output signal from the pertinent triport UPS 1 coincides with the detection output signals from the other triport UPS's 2 and 3. When the detection output signals from the other two triport UPS's 2 and 3 coincide 4 with each other and the detection output signal from the 0 0 pertinent triport UPS 1 differs from the other detection output signals, the two exclusive OR circuits 55 and 56 each produce an output and an AND circuit 57 consequently produces an output Since the outputs of an AND circuit 57 and a timer circuit (or delay circuit) 58 are fed to an AND circuit 59, the AND circuit 59 produces an output when the abnormal state of the pertinent triport continues beyond the prescribed duration. The output constitutes itself a release c*ut

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signal F for opening the paralleling switch Fig. 4 is a block diagram illustrating a specific configuration of the parallel synchronizing signal generating circuit 41.

A pulse generating circuit (such as, for example, a oneshot multivibrator) 61 is supplied a rectangular wave output from the oscillating circuit 29 and generates a trigger pulse synchronized to the leading-edge of the corresponding rectangular wave. Other pulse generating circuits 62 and 63 ,10 are similarly supplied the rectangular wave outputs from the oscillating circuits (not shown) of the other two triport UPS's 2 and 3 to generate a trigger pulse synchronized to the leading-edge of each of the rectangular waves.

The trigger pulses are paired and fed into AND circuits t' 15 65 to 67. In the present embodiment, therefore, any of the AND circuits 65 to 67 produces an output when the phases of the rectangular waves fed out of the oscillating circuits of any two of the three triport UPS's 1, 2 and 3 coincide with each other.

20 The pulses fed out of the AND circuits 65 to 67 are Spplied through an OR circuit 68 to the IN (inverter) terminal of the changeover switch 28 and serve as trigger pulses for the oscillating circuit 29 common to all of the triport UPS's 1,2 and 3 under parallel operation while the operation is proceeding in the inverter mode.

In the manner described above, the synchronization In the configuration of Fig. 4, a logical multiplication may not be normally operated due to the phase deviation mentioned above when the trigger pulses fed out of pulse generating circuits 61 to 63 happen to have an unduly small width (less than the level of about 6 to 10 ps, for example). Desirably, this trouble is corrected by setting the output pulse width of the pulse generating circuits 61 1 to 63 in advance to a suitably large size (200 ps, for example), driving an additional pulse generater (not shown) t t r to produce trigger pulses with narrower width in response to the output pulses from the OR circuits 68, and feeding the t-igger pulses with narrower width to the IN terminal of the changeover switch 28.

Fig. 5 is a block diagram illustrating a specific configuration of a synchronization monitoring circuit 43.

*Sao The rectangular wave outputs from the oscillating circuits 29 of the pertinent triport UPS 1 and the other $111a1 triport UPS's 2 and 3 under parallel operation are paired and fed to two-input exclusive OR circuits 71 and 72.

The exclusive OR circuits 71 and 72 produce no output and consequently the synchronization monitoring circuit 43 produces no output while the phase of the output from the oscillating circuit 29 of the pertinent triport UPS 1 coincides with that of the outputs from the oscillating (4circuits of the other two triport UPS's 2 and 3.

When the phase of the output from the oscillating circuit 29 of triport UPS 1 deviates from that of the outputs from the oscillating circuits of the other two triport UPS's 2 and 3, the outputs of the pair of exclusive OR circuits 71 and 72 are and, therefore, an AND circuit 73 produces as an output.

The output from the AND circuit 73, similarly to the case of the operation mode monitoring circuit shown in St 10 Fig. 3, is applied to a timer circuit (or delay circuit) 74 et and, then, the both outputs from the AND circuit 73 and the tt*« timer circuit 74 are fed to an AND circuit As the result, the AND circuit 75 produces an output when the state in which the output of the oscillating circuit 29 deviates from that of the other triport UPS's 2 and 3 continues beyond the prescribed duration, and said rt** output is used as a parallel-off or release signal F for pt opening the paralleling switch Generally, the exclusive logical operation for the monitoring of synchronization during the parallel operation It t f L of plural triport UPS's can be suitably set in accordance with the idea described above. Since the possibility of a plurality of triport UPS's simultaneously developing a deviation of phase is very low, however, it is practically sufficient to monitor the synchronization between the one particular triport UPS as an object of monitoring and each of the remaining triport UPS's.

Now, the operation of the embodiment of this invention so far described will be explained below.

The starting of the component triport UPS 1 of the parallel operation system according to the invention is attained by the conventional sequence control for starting as described below.

When the commercial and DC power source breakers (not shown) on the input sides of the triport UPS 1 are off, the 4 10 line switch 23, the inverter switch 24, and the paralleling switch 35 are invariably off, and the inverter 26 is at *t rest, the power source for the control circuit of the t triport UPS 1 is turned on. Consequently, the oscillating circuit 29 is triggered by an internal reset signal and begins to oscillate at a frequency substantially equal to the commercial power source frequency.

The inverter 26 is started by closing the breaker of the DC power source on the input side of the UPS 1.

I I Since the inverter switch 24 is simultaneously turned on, the triport transformer 22 is excited.

t C When the breaker of the commercial power source on the input side of the UPS 1 is closed, the oscillating frequency of the oscillating circuit 29 is lowered to a value slightly lower than the rated frequency of the commercial power source. When the phase of the rectangular waves output from the oscillating circuit 29 coincides with that of the AC 4 input, the oscillating circuit 29 begins to be controlled by the zero cross signals from the AC input synchronizing signal generating circuit 27 and starts generating rectangular waves perfectly synchronized with the AC input.

After the synchronization of the inverter 26 and the input commercial power source is confirmed in the manner described above, the line switch 23 is turned on on the condition that the inverter monitoring circuit 32 has detected that the inverter 26 is normally operating.

10O At the same time, the mode controlling circuit 39 0 @4 controls the phase shifter 30 to delay the phase of the ft 4 rectangular waves produced by the oscillating circuits 29 so t4* that the current detected by the inverter current detector 37 is zero, namely the inverter 26 is prevented from bearing the load current. As the result, the triport UPS 1 starts o operating in the normal mode.

The other triport UPS's 2 and 3 are started and set operating in the normal mode as described above. Since the 400 •times required for starting the individual triport UPS's are :20 not uniform, the parallel operation of these triport UPS's necessitate the following particular control sequence for their start.

In the configuration illustrated in Fig. 1, for example, when it is first confirmed that the triport UPS's 1 and 2 have assumed the normal mode, the corresponding paralleling switches 25 are simultaneously closed to start 4 r7 the parallel operation of these two triport UPS's 1 and 2.

Next, when the triport UPS 3 subsequently assumes the normal mode, the paralleling switch 25 corresponding to the UPS 3 is closed to complete the normal mode parallel operation of the three triport UPS's 1, 2 and 3.

At this time, all of the triport UPS's are perfectly synchronized because the oscillating circuits 29 of all triport UPS's 1, 2 and 3 are driven by the trigger pulses ,synchronized with the zero cross signal of the single a 11O commercial power source which is common AC input.

4 In cases where the inverters in the three triport UPS's It *fl 1 to 3 under the normal mode parallel operation described tt above are invariably normal and the commercial power source 9 serving as AC input is also normal, the AC input monitoring circuit 34 illustrated in Fig. 2 produces the signal "1" 1 indicative of the normality of AC and the changeover switch 28 is connected to the AC terminal as illustrated.

4 0 B The AC input synchronizing signal generating circuit 27 4o 9 produces trigger pulses synchronized with the zero crosses ,20 of the commercial power source voltage and consequently causes the oscillating circuit 29 to produce rectangular waves of the same phase as the zero crosses of the commercial power source voltage.

The rectangular waves produced by the oscillating circuits in the triport UPS's 1, 2 and 3 have identical phases because the oscillating circuits in the other two

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triport UPS's 2 and 3 parallel operating produce the rectangular waves in the same phases as the zero crosses of the commercial power source voltage.

As the result, the pulse generating circuits 61 to 63 of the parallel synchronizing signal generating circuits 41 generate in-phase trigger pulses which are fed to the IN terminal of the changeover switch 28.

As clearly noted from the description given above, the two sets of trigger pulses issued from the AC input 10 synchronizing signal generating circuit 27 and the parallel "404 synchronizing signal generating circuit 41 are perfectly ,r *synchronized and in-phase each other.

The outputs of the AND circuits 51 to 53 in the operation mode monitoring circuit 38 are invariably "l's" because the outputs from the AC input monitoring circuits 34 in all of the triport UPS's 1, 2 and 3 under parallel operation, namely the inputs to the operation mode monitoring B circuits 38, are all identical.

As the result, the mode controlling signal produced 1 20 from the OR circuit 54 is and the mode controlling circuit 39 closes the line switch 23 and, at the same time, controls the phase shifter 30 to cause the inverter driver 31 set the inverter 26 in the standby state. To be more specific, the phase of the reactangular waves produced from the oscillating circuits 29 is delayed so that the input current to the inverter 26 is kept at zero and the inverter 7 I 91 4 4 444* t 4 4 4 I Iii 4t 4 14 4 0 4 4 9 4444 414611 26 is prevented from bearing the load current. The control of such kind is well known to persons of ordinary skill in the art. At this time, the inverter switch 24 is kept in the ON state.

In the meantime, the outputs from the two exclusive OR circuits 55, 56 in the circuit 38 are and the output from the synchronization monitoring circuit 43 is also It follows that the paralleling signal F which is the output from the operation mode monitoring circuit 38 and the synchronization monitoring circuit 43 are also with the result that the paralleling switch 25 is retained in the closed state.

The normal mode parallel operation of the triport UPS's 1, 2 and 3 is carried out as described above. While the AC input is in normal, since the inverter is held in the standby state (with the input current thereof is zero), substantially all load current is supplied to the load from the commercial power source 9 through the line switch 23 and the triport transformer 22. Further at this time, the storage battery 10 is charged from the commercial power source 9 through the charger 12. Of course, the storage battery 20 may be replaced with some other suitable DC power source.

When the AC input monitoring circuit 34 develops an abnormality during the course of the normal mode parallel operation described above, the exclusive OR circuits 55 and

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56 and the AND circuit 57 of the operation mode monitoring circuits 38 respectively generate the outputs and, after the outputs have lasted beyond the prescribed duration, the parallel-off signal F is issued. As a consequence, the paralleling switch 25 is opened and the pertient triport UPS 1 is released from the parallel operation.

When the inverter 26 develops an abnormality, the inverter monitoring circuit 32 which compares the inverter drive signal and output signal of the inverter 26 issues 09000 0 0 o o a signal of abnormality. As the result, the inverter switch 00oo o o 00 S° 24 and the paralleling switch 25 are opened and the triport o*C 00 UPS 1 is released from the parallel operation.

00 4o <o The effective power P of the triport UPS is represented 0 by the following formula P VO-V1 Sin /wL (1) to o 4 0 In the formula, VO stands for the output voltage, VI o a ge for the input voltage, 9 for the phase difference between the input and output voltages, L for the leakage inductance 20 of the triport transformer, and w for the angular frequency.

The effective power of the triport UPS is inversely proportional to the leakage inductance. By making the leakage inductances of the triport UPS's under parallel operation inversely proportionated to their output capacities, RA4/.

the inverter capacities of the triport UPS's under parallel operation without requiring any special load control means.

Once the setup mentioned above is established, even when one of the plurality of triport UPS's under parallel operation develops abnormality, the parallel operation can be continued with proper allocation of load without employing any special control means (such as, for example, means for readjusting the load allocation).

When the commercial power source 9 fails during the course of the normal mode parallel operation, the AC input S" monitoring circuit 34 of the triport UPS 1 issues an AC v ,abnormal signal with the result that the changeover switch 28 is turned from the AC side to the IN side and the oscillating circuit 29 begins to be driven by trigger pulses from the parallel synchronizing signal generating circuit 41.

4 9 Since the trigger pulses on the AC side and on the IN side have been controlled so as to posess perfectly 4 identical phases as described above, the phase of the rectangular waves produced by the oscillating circuit 29 is not varied but allowed to maintain continuity.

When the AC abnormal signal is issued, the AND circuits 51 to 53 and the OR circuit 54 in the operation mode monitoring circuit 38 produce the output of and the mode controlling circuit 39 opens the line switch 23 22 and, at the same time, switches the inverter 26 from the standby mode to the operation mode or the inverter mode.

Specifically, the phase shifter 30 is controlled so as to nullify the phase delays of the rectangular waves produced by the oscillating circuits 29, in other words, to equalize the phase of the rectangular waves to that of the commercial power source 9 prior to the occurrence of the abnormality and the inverter 26 is thereby caused to feed a load current equal to that had been borne by the AC 10 input commercial power source prior to the occurrence of *4 t 6 the abnormality. The control of such kind is well known to 'elt persons of ordinary skill in the art.

In the meantime, the outputs from the exclusive OR circuits 55 and 56 and the AND circuits 57 and 59 of A '15 the operation mode monitoring circuit 38 are invariably I 44 unaltered and the output from the synchronization monitoring circuit 43 is not altered. Thus, any action for opening the paralleling switch 25 is not carried out.

When the abnormality occurs in the AC input as described above, all of the triport UPS's 1 to 3 are simultaneously switched from the standby mode to the inverter mode to establish the state of inverter mode parallel operation.

The switching to the inverter mode parallel operation in response to the abnormality in the AC input is attained substantially instantaneously on all of the paralleling 23 triport UPS's because the detection of abnormality in the AC input is carried out early and quickly. Thus there are no needs of consideration about the allocation of the load upon the triport UPS's during the course of the switching.

When the AC input is restored and the normal mode parallel operation is resumed during the course of the inverter mode parallel operation, since the discernment of the restoration of the normality of the AC input calls for lt, I a relatively long time and the time required for said ,i 10 discernment often varies between the triport UPS's, there is *the possibility of the allocation of load to the triport «UPS's losing balance.

The possibility mentioned above will be described below with reference to Fig. 6. Fig. 6 represents an equivalent circuit of the paralleling power source shown in Fig. 1 at the time when, in the triport UPS 1, the line switch 23 is turned on and the inverter 26 has not yet assumed the standby state and the output thereof is in-phase with the commercial power source, while the triport UPS's 2 and 3 have been already shifted to the normal mode (with the corresponding inverters in the standby state).

For the sake of simplicity of the explanation, it is assumed that all of the triport UPS's 1 to 3 possess equal capacities and, consequently, the leakage inductances formed by the magnetic shunts 22d, 22e of the triport transformers 22 are set at equal magnitude L. On said assumption, the

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24- -28- internal impedance of the triport UPS 1 is one half of that of the triport UPS's 2 or 3.

Since the load borne by each of the triport UPS's is inversely proportional to the magnitude of the leakage inductance thereof as described above, the triport UPS 1 is destined to bear twice as much power as the other triport UPS's 2 or 3. Thus, there ensues the disadvantage that t t" the applications of load cease to be proportional to the capacities of the triport UPS's.

Moreover, since the voltage stabilizer 351 of the triport UPS 1 suffers from an unduly increased burden, the voltage stabilizers 352 and 353 of the other triport UPS's 2 and 3 function to assist the voltage stabilizer 351 under the heavy load and consequently induce flow of a reactive current between the triport UPS's 1, 2 and 3. The reactive current not only causes a loss ii, the paralleling power i Ssource devices but also jeopardizes the stability of the Ssystem.

The operation mode monitoring circuit 38 of the present invention serves to preclude the disadvantageous phenomenon described above. To be specific, the AND circuits 51 to 53 and the OR circuit 54 in the operation mode monitoring circuit 38 issue a mode control signal when the prescribed number in all of the triport UPS's under parallel operation are switched from the inverter mode to the normal mode.

Thus, all of the triport UPS's under parallel operation are 1 k I simultaneously shifted to the normal mode by the same timing.

In the embodiment described above, the triport transformer 22 have been described as being provided with the magnetic shunts and causing the leakage inductance produced thereby to be utilized as the DC inductance.

Optionally, the triport transformers 22 may be provided with external reactance elements.

The operation mode monitoring circuits 38 and the t parallel synchronizing signal generating circuits 41 have *e been described as being installed severally in the individual triport UPS's. Optionally, a single operation mode monitoring circuit and a single parallel synchronizing signal generating circuit may be disposed so as to be commonly used by all of the triport UPS's in paralleling.

In the embodiment of Fig. 2, the magnetic core of the transformer 22 is described as being divided by the pair of magnetic shunts 22d, 22e into three section, with the output winding 22c formed in the central section. When the output winding is formed in a terminal section as disclosed in U.S.

Patent 4,556,802 which has been assigned to the present assignee, for example, the control of the shift of the triport UPS between the normal mode and the inverter mode can be carried out simply and accurately.

The preceding embodiments have been described as using independent transformers for each three phases. Optionally, the magnetic cores thereof may be formed in the shape of a triangular prism (or a delta-form) as disclosed in the specification of U.S. Serial No. 213257 which has been assigned to the present assignee, for example.

Specifically, the three transformers for three phases are arranged substantially along the edges of a triangular prism in such a manner that the rectangular magnetic cores of any two adjacent transformers will be disposed parallelly to each other to form three paired legs. Then a common winding 10 is formed on the three paired legs.

In the configuration of Fig. 7 w!ich is a quotation S A/o. t,?02,6S from the drawings of the U.S. Serial No. 213,257, three transformers TS1 to TS3 are each formed of a rectangular frame-shaped iron (or magnetically permeable) core each having a corresponding pair of magnetic shunts MS11 and MS12, MS21 and MS22, or MS31 and MS32 (which are partly hidden in the diagram) to thereby form three winding o sections or windows.

These transformers are placed together approximately in the shape of three faces of a triangular prism so that the adjacent leg parts of two of the three transformers will stand side by side as illustrated in Figure 7. Common windings are formed on adjacent pairs of legs for each of the three pairs of adjacent legs. Since the iron cores are each divided into three winding sections by pairs of magnetic shunts as described above, the windings are formed '7nr o 4 4 J 4j *4 41 14.r 4.

44 4..4 4.' 4.C i S with one in each pairs of adjacent winding sections for each adjacent pair of cores.

One set of output windings 91, 92, and 93 is formed in the corresponding second winding sections at the center of adjacent pairs of cores. Two sets of input windings 101 to 103 and 81 to 83 are formed, respectively, in the corresponding ones of the first adjacent winding section and in the corresponding ones of the third winding sections in the upper and lower parts of adjacent pairs of cores.

10 By applying common windings in the manner described above, one winding is allowed to function equivalently as two windings. In said setup, therefore, the number of windings can be reduced to one half that which is required when the windings are formed one each on the transformers.

Further, the phase deviations in the output voltages which occur when the power source or/and load are deprived of equilibrium can be decreased.

As is plain from the description.given above,Athis embodtl*e4V( A'14 invention bring about the following effects.

20 By having the leakage inductances (internal inductances) of the triport UPS's set in advance so as to be inversely proportional to the output capacities of the triport UPS's, the allocations of load current can be proportionated to the output capacities of the triport UPS's currently under parallel operation without requiring any special control means.

4is minimized because the phases of the oscillating circuit trigger pulses in all of the triport UPS's can be kept in-phase each other by the parallel synchronizing signal generating circuit.

The switching between the normal mode and the inverter 0 mode can be effected simultaneously on all of the e, triport UPS's, based on a proper prescribed logic operation (such as, for example, the rule of decision by majority or the coincidence above a stated level) lift performed on the mode discriminating signals from the triport UPS's. Thus the unbalance of the allocations of load, the occurrence of the circulating current, I t4 the unstability of the system, etc. due to the lack of coincidence in the switching timing can be precluded.

In the parallel-off of a particular triport UPS in trouble from the parallel operation, since the rate of increase of the short-circuit current in the case of short circuit, for example, can be suppressed by the leakage inductance (internal inductance) mentioned above, the time allowed for the detection of the short circuit or the parallel-off of the UPS in trouble can be lengthened and the structure of the detection and i 29 protection means can be simplified to ensure low cost and high reliability of the system.

The triport UPS's, by nature of their structure, are each provided with a series leakage inductance produced by a magnetic shunt of a three-winding transformer or a serially connected external series reactor. When a plurality of such triport UPS's are connected in parallel, therefore, the load currents borne by the individual triport UPS's are inversely proportional to the series leakage inductance of the triport UPS's as described more specifically herein elow.

When the magnitudes of the series leakage inductances or the external reactors 9t 9 are inversely proportionated to the output capacities of the individual triport UPS's, the load current by its inherent nature is apportioned proportionately to 15 the output capacities of the individual triport UPS's under parallel operation without requiring employment of any other means.

When a difference occurs between the output voltages of the inverters of the plurality of the triport UPS's under parallel operation, a circulating current 20 flows between the inverters. The circulating current is effectively prevented from being unduly increased because the serially connected inductances also function to suppress the circulating current.

The circulating current which is caused by a deviation of timing in the switching operation of the transistors between the inverters is limited to a relatively small value. The control of synchronization between the inverters and the control of constant output in each inverters do not require very high accuracy and the circuitry to be used for the control can be simplified.

901ZJkxlspe.012uduimu29 1 30 Further, when the triport UPS in trouble is to be released from the parallel operation, since the series leakage inductances suppress the rate of increase of the short-circuit current during a trouble of short circuit, for example, the time allowed for the detection of the short circuit or the parallel-off of the UPS in trouble is elongated. Thus, the device for parallel-off and protection of the UPS in trouble with low cost and high reliability can be easily materialized.

Owing to the provision of operating mode monitoring means capable of executing the logic operation on the output of detection from the AC input monitoring circuit of each of the triport UPS's, feeding the result of said logic operation as a mode control signal to the mode control means of each of the triport UPS's, and then, on detection of a difference between one and the remaining triport UPS's under parallel operation in their operating modes, issuing a parallel-off signal for causing the release of the said one UPS from the parallel operation, the switching from the inverter mode to the normal mode or vice versa can be carried out by one fixed timing on all of the triport UPS's in parallel operation. Thus, the inconveniences due to the difference of timing in the mode switching (occurrence of internal circulating current and instability of parallel operation) can be improved.

90112Jxbpc.O12 ir -Vh;3 7L KVT o,

Claims

1. Apparatus comprising at least one triport uninterruptable power source device connected, in use, between an AC input power source and a load and being adapted for connection in parallel with other triport uninterruptable power source devices, said at least one triport uninterruptable power source device comprising: a three-winding transformer having a first, a second and a third winding; an AC input connected to the first winding of the transformer through a first inductive component; an inverter connected to the second winding of the transformer through a second inductive component; an output terminal connected to the third winding of the transformer through a paralleling switch; ft.. an inverter driving means for driving the inverter in synchronization with the 15 ACinput; an AC input monitoring circuit for detecting normality or abnormality of the AC input; and a mode controlling means for controlling the switching of the inverter, in accordance with the output of detection from the AC input monitoring circuit, between S 20 a standby mode in which no output current is generated by the inverter and an inverter mode in which an output current is generated.

2. Apparatus according to claim 1, which further comprises an operation mode monitoring means for performing a logic operation on the output from the AC input monitoring circuit of said at least one triport uninterruptable power source device and feeding the result of the logic operation as a mode controlling signal to the mode controlling means.

3. An apparatus according to claim 1 or 2, wherein the inverter driving means includes an oscillating circuit. 9011cr2*xlaspc.i Aii =301 i I I I Ir I *4 S( SI. 32

4. An apparatus according to claim 3, wherein said oscillating circuit is adapted to be triggered by the zero cross point signal of the AC input voltage waveform, said inverter driving means further comprising a phase shifter for effecting phase shift of the output waveform fed out of the oscillating circuit, and an inverter driver for driving the inverter with the output of the phase shifter.

An apparatus according to claims 3 or 4, wherein said at least one triport uninterruptable power source device further comprises a parallel synchronizing signal generating means for executing a logic operation on the output of the oscillating circuit in each said at least one triport uninterruptable power source device and, on detection of abnormality in the AC input by the AC input monitoring circuit, feeding the result of the logic operation as a trigger pulse to the oscillating circuit.

6. Apparatus according to claim 3, 4 or 5, including a plurality of said triport uninterruptable power source devices connected in parallel, wherein at least one of said plurality of triport uninterruptable power source devices further comprises a synchronization monitoring means for executing a logic operation on the output of the oscillating circuit in each of the triport uninterruptable power source devices and, when the differences between the phase of the output from the oscillating circuit of 20 one of the triport uninterruptable power source devices and the phases of the outputs from the oscillating circuits of remaining triport uninterruptable power source devices exceed a prescribed level, issuing a parallel-off signal to open the paralleling switch of said one of the triport uninterruptable power source device.

7. An apparatus according to claim 2, including a plurality of said triport uninterruptable power source devices connected in parallel.

8. An apparatus according to claim 5, including a plurality of said triport uninterruptable power source devices connected in parallel. 901102,xlspe.012anihiu32 -33-

9. Apparatus according to claim 6 or claim 8, which further comprises an operation mode monitoring means for executing a logic operation on the output from the AC input monitoring circuit of each of the triport uninterruptable power source devices and feeding the result of the logic operation as a mode controlling signal to the mode controlling means.

Apparatus according to claim 7 or claim 9, wherein the operation mode monitoring means are disposed one each in the triport uninterruptable power sources.

11. Apparatus according to claim 7 or claim 9, wherein only one operation mode monitoring means is disposed commonly for the triport uninterruptable power sources. a

12. Apparatus according to any one of claims 6, 8, and 9, wherein the parallel %tit synchronizing signal generating means are disposed one each in the triport S 15 uninterruptable power sources.

13. Apparatus according to claims 6, 8, and 9, wherein only one parallel synchronizing signal generating means is disposed commonly for the triport uninterruptable power sources.

14. Apparatus according to claim 6 or claim 9, wherein the synchronization Smonitoring means are disposed one each in the triport uninterruptable power sources.

Apparatus according to claim 7 or claim 9, wherein the operation mode monitoring means executes a logic operation on the output of detection from the AC input monitoring circuit of each of the triport uninterruptable power source devices and, when the output of detection from the AC input monitoring circuit of one of the triport uninterruptable power source devices differs from the outputs of detection from the AC input monitoring circuits of the remaining triport uninterruptable power source devices, issues the results of the logic operation as a parallel-off signal for said one triport uninterruptable power source device. 901102,kxlspe.012ihmu33 e/VT 0 A 34

16. Apparatus according to any one of the preceding claims, wherein at least one of the first and second inductive components is a leakage inductance generated by the magnetic shunt formed on a magnetically permeable core of the three-winding transformer.

17. Apparatus according to any one of claims 1 to 15, wherein at least one of the first and second inductive components is an inductor connected in series to the corresponding input winding of the three-winding transformer.

18. Apparatus according to any one of claims 1 to 15 or claim 17, wherein the magnitudes of the first and second inductive components of each of the triport t Iuninterruptable power source devices are set so as to be inversely proportional to the respective output capacities of the triport uninterruptable power source devices.

19. Apparatus according to any one of claims 1 to 15 or claim 18, wherein the magnetically permeable core of the three-winding transformer is divided with two magnetic shunts into three sections including one central and two terminal sections and the third winding is formed on one terminal section and the first and the second windings are formed in the remaining two sections.

Apparatus according to any one of the preceding claims, wherein the output terminal has a voltage stabilizer connected thereto.

21. Apparatus according to any one of claims 1 to 16, wherein said at least one triport uninterruptable power source device is for three-phase configuration and three transformers are arranged substantially along the edges of a triangular prism in such a manner that the rectangular magnetically permeable cores of any two adjacent transformers will be disposed in parallel with each other to form three paired legs and a common winding is formed on each of the paired legs. LU 901102jaispe.012alblasMi /Vr f

22. riprt ninerrutabe pwersource apparatus substantially as hereinbefore described with reference to the drawings. DATED this 2nd day of November, 1990. NISHIMU ELECTRONICS INDUSTRIES CO., LTD. By its Patent Attorneys DAVIES COLLISON 901102,kxlape.012,injMU,35