AU598870B2

AU598870B2 - Memory access controller

Info

Publication number: AU598870B2
Application number: AU81445/87A
Authority: AU
Inventors: Minoru Abe; Kuniaki Kishino; Hiroshi Taguchi
Original assignee: Oki Electric Industry Co Ltd
Current assignee: Oki Electric Industry Co Ltd
Priority date: 1986-11-21
Filing date: 1987-11-20
Publication date: 1990-07-05
Anticipated expiration: 2007-11-20
Also published as: DE3751693D1; JPS63132369A; DE3751693T2; EP0269370A3; AU8144587A; CA1296808C; EP0269370A2; KR880006592A; EP0269370B1; KR920003174B1

Description

i;n 5988 1r 0 COMMONWEALTH OF AUSTRALIA PATENTS ACT 1952-69 COMPLETE

SPECIFICATION

(ORIGINAL)

Class Int. Class Application Number: Lodged: Complete Specification Lodged: So Accepted: Pr;crity SRelated Art: 0 Published: his doemlinJtcontn ai -th dflelldmelilts radc id.. r 4 Secioun 4(3 aiaJ is ccrnxt iI Name of Applicant: Address of Applicant: Actual Inventor: Address for Service: OKI ELECTRIC INDUSTRY CO., LTD.

7-12, Toranomon 1-chome, Minato-ku, Tokyo, Japan KUNIAKI KISHINO, MINORU ABE and HIROSHI TAGUCHI EDWD. WATERS SONS, 50 QUEEN STREET, MELBOURNE, AUSTRALIA, 3000.

Complete Specification for the invention entitled: MEMORY ACCESS CONTROLLER The following statement is a full description of this invention, including the best method of performing it known to us

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o c- c 0cC 000 O 0000 00 00O o' 0 0 0~ 0 o 0 4 a 4.i: MEMORY ACCESS CONTROLLER BACKGROUND OF THE INVENTION i. Field of the Invention: The present invention relates to a memory information transfer unit for transferring the information from one processing unit to another one.

2. Prior Art: Many information processing units transfer information from one unit to another or vica versa. Thereupon, each processing unit is needed to execute another operation without interruption of another operation during carrying out such information transfer or reception. For this purpose, the following conventional processing units are known: ones adapted to effect transmission and reception as well as processings therein in time sharing from the beginning, ones adapted to wait and effect information transmission and reception when there is no requirement for processing in themselves, and ones adapted to transfer any information written in an area of a memory to another unit by using a data channel device while they do not access the memory.

However, those processing units arranged as described above took much time to perform internal processing or required a complicated external control apparatus. In addition, with a large amount of information to be transferred, a large amount of transfer time was needed from the start to the end of that transfer.

SUMMARY OF THE INVENTION In view of the drawbacks of the prior art, it is an object of the present invention to provide a memory access controller for controlling information transfer from one processing unit from among a plurality of processing units to another processing unit from among the plurality of processing units using the same memory.

Another object of the present invention is to provide a memory access controller capable of processing for transmission and reception for a short period of time with ease as well as of another processing even during the transmission and reception.

0 Q0 a To achieve the above object, a memory access controller for controlling a transfer of information from one processing unit from among a plurality of processing units to another processing unit from among said plurality of processing units, each of the plurality processing units has a processing bus, said memory access controller comprising: a buffer memory means, contained within said memory access controller, for storing information to be transferred; a control means for controlling write and read operations into and out of said buffer memory means in accordance with a pulse signal having a predetermined continuous period; a selection means for selecting processing units from among said plurality of processing units one after another on the basis of a predetermined selection reference protocol when a plurality of processing units transmit write or read requests to said buffer memory means within said predetermined period; a communication means for informing those of said plurality of processing units which have transmitted write or read requests within said predetermined period that said buffer memory means is being accessed; a plurality of data latch means for latching data contained within data bus signals transmitted from said buffer memory means to each of said processing units, wherein the quantity of data latch means is equal to the quantity of said plurality of processing units; and a plurality of connection means for separately connecting said memory access controller to each of the plurality of processing units via the processing bus of each of the plurality of processing units.

The above and other objects, features and L-7 advantages of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings in which a preferred embodiment of the present invention is shown by way of illustrative example.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit block diagram of an embodiment of a memory access controller according to the present invention; Figure 2 is an illustration showing the arrangement of a buffer memory; Figure 3 is a timing chart of a write operation by the embodiment of Figure 1; Figure 4 is a timing chart of a read operation by the embodiment of Figure 1; Figure 5 is a timing chart of a write operation when a preceding access instruction takes precedence; Figure 6 is a timing chart of a read operation of Figure Figure 7 is a timing chart of a write operation when a port P. takes precedence; and Figure 8 is a timing chart of an exceptional read operation when the port P 1 takes precedence.

DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 1 is a circuit block diagram of an embodiment of a memory access controller according to the a present invention.

As the figure shows, a plurality of processing oo units (not shown, and hereinafter referred to as units), which mutually transfer information, include respectively ports to which symbols P 1 and P 2 are assigned and possessed by respective signals as designations thereof.

Although the description here employs two processing units for brevity, the present invention is not limited thereto.

In addition, although a plurality of terminals are actually provided for each of signal terminals 13, 14, 18 and 3 d 19, and for address and data bus signal terminals of a buffer memory 30, they will hereafter be represented by single terminals, as the figure shows.

A buffer memory 30, memory means, can write therein and read therefrom information on the basis of write and read requests from the respective ports Pi and P 2 Figure 2 is an illustration showing the configuration of an embodiment of the buffer memory 30. The buffer memory 30, a general purpose type of 8K words X 8 bits, comprises the total of 32 pages from No.

0 to No. 31. Each page includes 256 words, and each address is given in hexadecimal notation 0000 to 1FFF. High order 5 bits and low order 8 bits respectively correspond to the page number and the address number in each page. Those high order 5 bits are employed for specification of the buffer memory upon mutual information transfer between the ports Pi and P 2 Access timing setting sections 1 and 2, respectively designated 31 and 32, receive a pulse signal from a timing signal generator (not shown) at inputs thereof through a pulse signal terminal 20 at predetermined time instants B, C, E and so on, as shown in timing charts of Figures 3 to 8. Each of access timing setting section 31 or 32, when kept at a high level (hereinafter referred to as at an input D thereof, issues access timing signals TMA, and TMA 2 at an output Q thereof until their reception of the next pulse signal.

Access request latch sections 1 and 2 are respectively designated 33 and 34.

When either a P 1 write signal (a write request signal from the port P terminal 11 or a Pi read signal (a read request signal from the port Pi) terminal 12 changes to the access request latch section i, designated 33, changes its input C to via an OR gate 35, and changes its output Q to by the positive edge thereof. In the same fashion, when either a P 2 write signal terminal 16 or a P 2 read signal terminal 17 changes to the access request latch section 2, designated 34, changes its input C to via an OR gate 36, and changes its output Q to by the positive edge thereof.

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CC 0, CC 04 CO 44 44 4i kv- .9 An access port selector section, designated 37, identifies a signal level at the output Q of each of the access request latch part 33 and 34, and changes only one of its outputs Al anid A2 on the basis of a predetermined selection reference protocol described later before the pulse signal at the pulse signal terminal 20 becomes "H" The access timing setting sections 31 and 32 sample the signal at their respective inputs D with the positive edge at the time instant of C to provide their respective outputs Q, and keep that state until the positive edge of the pulse signal at the next time instant of C.

The access request latch sections 33 and 34, when the output Q of each of the access timing setting parts 31 and 32 becomes input the positive edge thereof through their reset terminals R and are thereby reset.

o An OR gate 38 changes a P 1 in-access display signal terminal 10 to as the port P 1 being accessed while the access request latch section i, designated 33 or the access timing setting section 1, designated 31 stays at at their °i outputs Q, and indicates to the unit P that the port PI is o accessed to the buffer memory.

Likewise, an OR gate 39 changes a P 2 in-access display signal terminal 15 to as the port P 2 being accessed while the access request latch section 2, designated 34 or the access timing setting section 2, designated 32, stays at at uo .their outputs Q, and indicates to the P 2 is accessed to the SO buffer memory.

oo~ A tri-state buffer 40 (although a plurality of tri-state buffers of the same type are employed, a single tri-state buffer is here depicted instead for brevity) outputs S p 1 address signals 13 as address signals ADM of the buffer memory 30 when the access timing setting section i, designated 31, has its output Q at Likewise, a tri-state buffer 41 (although a plurality of tri-state buffers are actually employed as in the case of the tri-state buffer 40, a single tri-state buffer is here depicted instead for brevity) outputs a P 2 address signal 18 as the address signal ADM of the buffer memory 30 when the access timing setting section 2, designated 32, has its output Q at An AND gate 42 becomes when the P 1 write signal terminal 11 is at and the access timing setting section i, designated 31, has its output Q kept at "H" With the AND gate 42 having its output at it provides information at the P 1 data bus signal terminal 14 to the buffer memory 30 as a data bus signal DATAM via the tri-state buffer 43.

Simultaneously, the AND gate 42 provides a write signal WM to the buffer memory 30 via an OR date 44, and writes the content of the data bus signal DATA M in the buffer memory at that time at that time at a specified address AD

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thereof.

thro.An AND gate 45 likewise becomes when a P 2 write signal terminal 16 is at and the access timing setting section 2, designated 32, has its output Q kept at With the AND gate 45 having its output at it provides information at a P2 data bus signal terminal 19 to the buffer memory 30 as the data bus signal DATA M via a tri-state buffer 46. The AND gate 45 simultaneously provides a write Ignal WM to the buffer memory 30 via an OR date 44, to thereby write the content of the data bus signal DATA M of the buffer memory 30 at that time in the buffer memory 30 at a specified address ADM thereof.

An AND gate 47 has its output changing to when the P 1 read signal terminal 12 is at and the access timing setting section i, designated 31, has its output Q at The AND gate 47, once becoming provides an o output enable signal RM to the buffer memory 30 via an OR gate o 48. Thereupon, the operation provides in the same manner as in the write operation described previously, the information at the P 1 address signal terminal 13 as the address signal ADM of the buffer memory 30 via the tri-state buffer 40 to read the word content in the buffer memory 30 at the address AD 6 Likewise, an AND gate 49 has its output changing to when a P 2 read signal terminal 17 is at and the access timing setting section 2, designated 32, has its output Q at The AND gate 49, once becoming provides an output enable signal RM to buffer memory 30 via an OR gate 48.

Thereupon, this enables information at the P 2 address signal terminal 18 to be provided as the address signal ADM of the buffer memory 30 via the tri-state buffer 41 whereby the word content in the buffer memory 30 at the address AD M thereof is read.

Data latch sections 1 and 2, designated 50 and 51 and employed in the read operation, receive the data bus signal read from the buffer memory 30 at their respective input terminals DINS. The respective data latch sections 1 and 2, I designated 50 and 51, receive a latch timing by driving the inverters 52 and 53 with negative edges of outputs from the AND gates 47 and 49 to latch the content of the data bus signal, and output that data bus signal DATAM from the output terminals D OUTS Buffers 54 and 55 feed data at the output terminals DoUTs of the respective data latch sections 50 and 51 to the terminals 14 and 19 respectively as the P 1 data bus signal and the P 2 data bus signal when the P 1 and P 2 readd signal terminals 12 and 17 are respectively at "H" In succession, operation of the embodiment of Figure 1 will be described.

Figure 3 is a timing chart of a write operation upon information being transferred from the port P 1 unit to the buffer memory First, when the P 1 unit issues the P 1 write signal at the time instant A of Figure 3, the P 1 write signal terminal 11 of Figure 1 (W 1 of Figure 3) becomes Slightly thereafter, the access request latch section 1, designated 33, changes its output Q to to cause the P 1 in-access display signal terminal 10 (DISP 1 to become 7 A 1 x I §1 I? l.

whereby the memory access controller displays that the P, unit is accessed. The access port selection section 37 changes Ii its output Al to owing to the access request latch section 1, designated 33, becoming at its output Q.

The access timing setting section 1, designated 31, has its input terminal D becoming and receives a pulse signal at its pulse signal terminal 20 at the time instant of B to cause TMA 1 the access timing signal at its output Q, to become The write signal WM of the buffer memory becomes upon receiving the access timing signal, Then, information (ADi) at the Pi address signal terminal 13 involving the page number as the address signal of the buffer memory is provided as the address signal ADM of the buffer memory 30. In addition, the information (DATA 1 at the Pi data bus signal terminal 14 as transfer data is provided as the data bus signal DATAM of the buffer memory With the passage of a predetermined access period (a period from the time instant B to C of Figure the access timing signal TMA, changes to to result in the end of the information write operation.

The port Pi unit confirms the end of the write operation based upon the DISPl signal becoming at the time instant C, and thereby changes the Pi write signal W 1 to at the time instant D.

Figure 4 is a timing chart showing a situation in which the port P 2 unit reads the associated information stored a in the buffer memory 30. First, once the P 2 unit issues the P 2 So read signal at the time instant A of Figure 4, the terminal 17 of Figure 1 (R 2 of Figure 4 (becomes Immediately thereafter, the access request latch section 2, designated 34, I becomes at its output with the P2 in-access display signal terminal 15 (DISP 2 becoming whereby tlie memory access controller indicates the P 2 unit to be in accessed. The access port selection section 37 changes to at its output A 2 in response to the access request latch section 2, designated 34, becoming at its output Q.

8 O. The access timing setting part 2, designated 32, permits the access timing signal TMA 2 at its output Q to become at the time instant B of Figure 4. As a result, the buffer memory 30 permits the output enable signal RM to become In succession, the information (AD 2 at the P 2 address signal terminal 18 for addressing the buffer memory is provided as the address signal ADM of the buffer memory The data latch section 2, designated 51, receives the information (DATA read from an address specified by the P address signal AD 2 The access timing signal TMA 2 becomes at the time instant C, and hence the information read operation from the buffer memory 30 is completed and the P 2 in-access display signal DISP 2 becomes Simultaneously, the data latch section 2, designated 51, latches the aforementioned read data bus signal DATAM and transfers the same as the P 2 data bus signal DATA 2 from the terminal 19 to the P 2 unit. The fact of the DISP 2 signal becoming indicates that the P2 data bus signal DATA 2 has effectively read transmitted data.

The port P 2 unit, once reading that read transmitted data, changes the P 2 read signal to at the time instant D to complete the read operation from the memory.

Figure 5 is a timing chart for write operation when a processing unit, which issues an access instruction earlier than the other processing units, is assumed to have priority.

Description of each signal on the side of the buffer memory will be omitted here. A situation is illustrated here that the P write signal W1 becomes at the time instant A of the same figure, and successively the P 2 write signal W 2 becomes at the time instant and then the access timing setting sections 31 and 32 receive a pulse signal at their input terminals C from the pulse signal terminal The access request latch sections 33 and 34 respectively become at their outputs Q at the time instants A and A' to result in both of the signal DISP I at the P.

in-access display signal terminal 10 and the signal DISP 2 at 9

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the P2 in-access display signal terminal 15 becoming "H" The access port selection section 37 changes to "H" at its output A. before the time instant B in response to the Pi write signal W. issued previous to the P2 write signal W 2 As a result, the access timing setting section i, designated 31, receives the pulse signal from the pulse signal terminal 20 at the time instant B and issues the access timing singal TMA.. In response to the TMA 1 becoming the access request latch section i, designated 33, changes to at its output Q. The access port selection section 37 changes to "L" at its output A 1 and to at its output A 2 before the time instance C. Thereafter, the access timing setting section 2, designated 32, receives the pulse signal from the pulse signal terminal 20 at the time instant C to change the TMA 2 signal to For the write operation in the buffer memory the Pi data bus signal DATA 1 is written at an address specified by the AD 1 in the period of the access timing TMA kept at in the same manner as in the timing chart of Figure 3.

Likewise, the P2 data bus signal DATA 2 is written in the buffer memory 30 at an address specified by the AD 2 in the period of the access timing TMA 2 kept at These write operations are completed respectively at the time instants D and D' Figure 6 is a timing chart for the read operation in an situation where a processing unit, which issues an access instruction earlier than the other processing units, takes precedence. In this case, the P 2 read signal R 2 precedes the I Pi read signal The buffer memory 30 permits data at an address specified by the P 2 address signal AD 2 to be read therefrom in the period of the access timing signal TMA 2 kept at and the data latch section 2, designated at 51, latches data contained in the data bus signal DATA m at the time instant

C.

Likewise, the buffer memory 30 permits data at an address specified by the Pi address signal AD 1 to be read therefrom in the period of the access timing signal TMA 1 kept VisV at and the data latch section i, designated at 50, latches data contained in the data bus signal DATAM at the time instant

E.

The operation thereafter proceeds in the same fashion as in Figure 4. That is, the respective data latch sections transmits those data latched therein as the P 2 X data bus signal DATA 2 and the P 1 data bus signal DATA 1 via the tri-state buffers 55 and 54.

Figure 7 is a timing chart of the write operation when the port Pi takes precedrnce over the port P2 The P 1 write signal W 2 is issued earlier than the Pi write signal. The access port selection section 37 detects the P. write signal W 1 having priority before the time instant B, and giving priority thereto to change its output Al to The access timing setting section 1 therefore permits the TMA 1 the output Q thereof, to become first.

00 soo The access port setting section 37 thereafter ouo changes its output A to and its output A2 to before the time instant C. At the time instant C, the TMA 1 the 00-..00 signal at the access timing setting section 1, designated at oo, 31, is changed to while the TMA 2 the signal at the access timing setting section 2, designated 32, is changed to Thereafter, the write operation in the buffer memory proceeds in the same fashion as in the write timing in Figure o 3.

Figure 8 is a timing chart of the read operation in a situation where the port P 1 takes precedence over the port S, o P2" In this situation, however, the P2 read signal R 2 is O issued before the time instant B, while the P 1 read signal R.

is issued after that time instant. Accordingly, the port P 1 although having priority, does not take precedence, and permits the access timing signal TMA, cn the side of the port P 2 to change to at the time instant B, whereby the read operation by the port P 2 is executed in the same manner as that of Figure 4. At the time instant C, the access timing signal TMA I on the side of the port P 1 becomes to permit the port 1 to execute the read operation.

According to the present invention, as described above, a relatively simplified memory access controller can be constructed using a general-purpose memory. Furthermore, the access controller can be accessed from a plurality of processing units simultaneously.

Although the invention has been described in its preferred forms with a certain degree of particularity, it is a matter of course that many changes and variations are obviously possible. It is therefore to be understood that the invention may be practiced otherwise than as specifically described without departing from the scope and spirit thereof.

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Claims

1. A memory access controller for controlling a transfer of information from one processing unit from among a plurality of processing units to another processing unit from among said plurality of processing units, each of the plurality of processing units has a processing bus, said memory access controller comprising: a buffer memory means, contained within said memory access controller, for storing information to be transferred; a control means for controlling write and read operations into and out of said buffer memory means in accordance with a pulse signal having a predetermined continuous period; a selection means for selecting processign units from among said plurality of processing units one after another on the basis of a predetermined selection reference protocol when a plurality of processing units transmits write or read requests to said buffer memory means within said predetermined S.period; a communication means for informing those of said plurality of processing units which have transmitted write or read requests within said predetermined period that said buffer memory means is being accessed; a plurality of data latch means for latching data o 2 contained within data bus signals transmitted from said buffer memory means to each of said processing units, wherein the 0 I o quantity of data latch means is equal to the quantity of said plurality of processing units; and a plurality of connection means for separately connecting said memory access controller to each of the plurality of processing units via the processing bus of each of the plurality of processing units.

2. A memory access controller according to claim 1, wherein said selection means preferentially selects a I Sprocessing unit from among said processing units which has transmitted an access request earlier than all other processing units from among said processing units which have also 'transmitted access requests.

3. A memory access controller according to claim 1, wherein said selection means accepts write or read requests from said plurality of processing units during a specific period and selects them in succession on the basis of a predetermined priority reference protocol for said plurality of processing units. Dated this 29th day of January, 1990. OKI ELECTRIC INDUSTRY CO., LTD. i o e WATERMARK PATENT TRADEMARK ATTORNEYS °i ^FLOOR 2, 290 BURWOOD ROAD, I o °HAWTHORN, VICTORIA, 3122, AUSTRALIA. o o o o 0 O" a