AU587947B2 - Synchronising apparatus for a digital signal demultiplexer - Google Patents

Synchronising apparatus for a digital signal demultiplexer

Info

Publication number
AU587947B2
AU587947B2 AU20193/88A AU2019388A AU587947B2 AU 587947 B2 AU587947 B2 AU 587947B2 AU 20193/88 A AU20193/88 A AU 20193/88A AU 2019388 A AU2019388 A AU 2019388A AU 587947 B2 AU587947 B2 AU 587947B2
Authority
AU
Australia
Prior art keywords
digital signal
bit
signal demultiplexer
slip
synchronising apparatus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU20193/88A
Other versions
AU2019388A (en
Inventor
Johann Magerl
Wilhelm Volejnik
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of AU2019388A publication Critical patent/AU2019388A/en
Application granted granted Critical
Publication of AU587947B2 publication Critical patent/AU587947B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0605—Special codes used as synchronising signal

Abstract

The object consists of equalising a bit slip during the demultiplexing of a multiplex signal. A bit-slip detection device (10) detects a bit slip and controls a clock frequency switching circuit (11) in such a manner that the number of the bits output to the outputs (4a-4d) of the demultiplexer (3) is returned to the nominal value by accelerating or decelerating the clock at the main frame counter (8). The invention is used in digital signal demultiplexers. <IMAGE>
AU20193/88A 1987-07-31 1988-07-29 Synchronising apparatus for a digital signal demultiplexer Ceased AU587947B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3725477 1987-07-31
DE3725477 1987-07-31

Publications (2)

Publication Number Publication Date
AU2019388A AU2019388A (en) 1989-02-02
AU587947B2 true AU587947B2 (en) 1989-08-31

Family

ID=6332834

Family Applications (1)

Application Number Title Priority Date Filing Date
AU20193/88A Ceased AU587947B2 (en) 1987-07-31 1988-07-29 Synchronising apparatus for a digital signal demultiplexer

Country Status (6)

Country Link
EP (1) EP0301481B1 (en)
AT (1) ATE75087T1 (en)
AU (1) AU587947B2 (en)
DE (1) DE3870073D1 (en)
ES (1) ES2030476T3 (en)
GR (1) GR3004923T3 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5241541A (en) * 1990-03-15 1993-08-31 International Business Machines Corporation Burst time division multiplex interface for integrated data link controller
FR2682842B1 (en) * 1991-10-18 1994-07-22 France Telecom METHOD AND DEVICE FOR COUNTING CLOCK SLIDES.
FR2689709B1 (en) * 1992-04-01 1995-01-06 France Telecom Method for correcting uncontrolled slippage of data sequences carried by digital links and device for implementing this method.
DE10154252B4 (en) * 2001-11-05 2005-12-01 Siemens Ag Method for detecting and compensating for bit-slip errors in the serial transmission of digital data and circuit arrangement that can be used for this purpose on the receiver side
JP3945287B2 (en) * 2002-03-28 2007-07-18 日本電気株式会社 Data receiving circuit and data receiving method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0023331A1 (en) * 1979-07-27 1981-02-04 Siemens Aktiengesellschaft Circuit arrangement for the synchronization of a subordinate device, in particular a digital subscriber station, by a higher order device, in particular a digital switching exchange of a PCM telecommunication network

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3212450A1 (en) * 1982-04-02 1983-10-13 Siemens AG, 1000 Berlin und 8000 München SYNCHRONIZING DEVICE OF A DIGITAL SIGNAL DEMULTIPLEX DEVICE
EP0134374B1 (en) * 1983-09-07 1987-12-02 International Business Machines Corporation Phase-locked clock

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0023331A1 (en) * 1979-07-27 1981-02-04 Siemens Aktiengesellschaft Circuit arrangement for the synchronization of a subordinate device, in particular a digital subscriber station, by a higher order device, in particular a digital switching exchange of a PCM telecommunication network

Also Published As

Publication number Publication date
EP0301481B1 (en) 1992-04-15
ATE75087T1 (en) 1992-05-15
ES2030476T3 (en) 1992-11-01
AU2019388A (en) 1989-02-02
DE3870073D1 (en) 1992-05-21
GR3004923T3 (en) 1993-04-28
EP0301481A1 (en) 1989-02-01

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