AU5680480A - Clock recovery device - Google Patents

Clock recovery device

Info

Publication number
AU5680480A
AU5680480A AU56804/80A AU5680480A AU5680480A AU 5680480 A AU5680480 A AU 5680480A AU 56804/80 A AU56804/80 A AU 56804/80A AU 5680480 A AU5680480 A AU 5680480A AU 5680480 A AU5680480 A AU 5680480A
Authority
AU
Australia
Prior art keywords
recovery device
clock recovery
clock
recovery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU56804/80A
Other languages
English (en)
Inventor
Claude Athenes
Philippe Blouin
Jacques Edmond Salle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Le Materiel Telephonique Thomson CSF
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Le Materiel Telephonique Thomson CSF filed Critical Le Materiel Telephonique Thomson CSF
Publication of AU5680480A publication Critical patent/AU5680480A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/20—Repeater circuits; Relay circuits
    • H04L25/24—Relay circuits using discharge tubes or semiconductor devices
    • H04L25/242—Relay circuits using discharge tubes or semiconductor devices with retiming
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
AU56804/80A 1979-03-26 1980-03-25 Clock recovery device Abandoned AU5680480A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR7907536A FR2452828A1 (fr) 1979-03-26 1979-03-26 Dispositif de reconstitution d'horloge
FR7907536 1979-03-26

Publications (1)

Publication Number Publication Date
AU5680480A true AU5680480A (en) 1980-10-02

Family

ID=9223569

Family Applications (1)

Application Number Title Priority Date Filing Date
AU56804/80A Abandoned AU5680480A (en) 1979-03-26 1980-03-25 Clock recovery device

Country Status (7)

Country Link
US (1) US4327442A (enExample)
EP (1) EP0016678B1 (enExample)
AU (1) AU5680480A (enExample)
BR (1) BR8001800A (enExample)
DE (1) DE3066790D1 (enExample)
FR (1) FR2452828A1 (enExample)
GR (1) GR67741B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU631077B2 (en) * 1990-11-19 1992-11-12 American Telephone And Telegraph Company Method and apparatus for adaptively retiming and regenerating digital pulse signals

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1200896B (it) * 1985-12-18 1989-01-27 Sgs Microelettronica Spa Circuito di risincronizzazione di segnali impulsivi,particolarmente per periferiche di microprocessori
FR2646742B1 (fr) * 1989-05-03 1994-01-07 Telecommunications Sa Dispositif pour synchroniser un signal pseudo-binaire avec un signal d'horloge regeneree a sauts de phase

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3185963A (en) * 1960-11-25 1965-05-25 Stelma Inc Synchronizing system having reversible counter means
US3266024A (en) * 1962-05-31 1966-08-09 Ibm Synchronizing apparatus
US3576570A (en) * 1968-12-12 1971-04-27 Sperry Rand Corp Synchronous timing scheme for a data processing system
US3668315A (en) * 1970-05-15 1972-06-06 Hughes Aircraft Co Receiver timing and synchronization system
JPS5853809B2 (ja) * 1977-12-20 1983-12-01 日本電気株式会社 クロツクパルス再生回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU631077B2 (en) * 1990-11-19 1992-11-12 American Telephone And Telegraph Company Method and apparatus for adaptively retiming and regenerating digital pulse signals

Also Published As

Publication number Publication date
FR2452828A1 (fr) 1980-10-24
EP0016678A1 (fr) 1980-10-01
GR67741B (enExample) 1981-09-16
FR2452828B1 (enExample) 1983-08-05
BR8001800A (pt) 1980-11-18
DE3066790D1 (en) 1984-04-12
EP0016678B1 (fr) 1984-03-07
US4327442A (en) 1982-04-27

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