AU5325179A - Selectively clearing cache store - Google Patents

Selectively clearing cache store

Info

Publication number
AU5325179A
AU5325179A AU53251/79A AU5325179A AU5325179A AU 5325179 A AU5325179 A AU 5325179A AU 53251/79 A AU53251/79 A AU 53251/79A AU 5325179 A AU5325179 A AU 5325179A AU 5325179 A AU5325179 A AU 5325179A
Authority
AU
Australia
Prior art keywords
cache store
selectively clearing
clearing cache
selectively
store
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
AU53251/79A
Other versions
AU538678B2 (en
Inventor
John B. Crain
Ronald E. Lange
Thomas R. Ohlin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of AU5325179A publication Critical patent/AU5325179A/en
Application granted granted Critical
Publication of AU538678B2 publication Critical patent/AU538678B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0822—Copy directories

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU53251/79A 1978-12-11 1979-11-28 Selectively clearing cache store Ceased AU538678B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US96822378A 1978-12-11 1978-12-11
US968223 1978-12-11

Publications (2)

Publication Number Publication Date
AU5325179A true AU5325179A (en) 1980-06-19
AU538678B2 AU538678B2 (en) 1984-08-23

Family

ID=25513931

Family Applications (1)

Application Number Title Priority Date Filing Date
AU53251/79A Ceased AU538678B2 (en) 1978-12-11 1979-11-28 Selectively clearing cache store

Country Status (5)

Country Link
JP (1) JPS5580875A (en)
AU (1) AU538678B2 (en)
DE (1) DE2947115A1 (en)
FR (1) FR2444299A1 (en)
GB (1) GB2037466A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1159153A (en) * 1979-12-14 1983-12-20 Charles P. Ryan Apparatus for cache clearing
US4322795A (en) * 1980-01-24 1982-03-30 Honeywell Information Systems Inc. Cache memory utilizing selective clearing and least recently used updating
US4399506A (en) * 1980-10-06 1983-08-16 International Business Machines Corporation Store-in-cache processor means for clearing main storage
EP0051745B1 (en) * 1980-11-10 1988-01-27 International Business Machines Corporation Cache storage hierarchy for a multiprocessor system
DE3138972A1 (en) * 1981-09-30 1983-04-14 Siemens AG, 1000 Berlin und 8000 München ONCHIP MICROPROCESSORCHACHE MEMORY SYSTEM AND METHOD FOR ITS OPERATION

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3723976A (en) * 1972-01-20 1973-03-27 Ibm Memory system with logical and real addressing
JPS5440182B2 (en) * 1974-02-26 1979-12-01
US3979726A (en) * 1974-04-10 1976-09-07 Honeywell Information Systems, Inc. Apparatus for selectively clearing a cache store in a processor having segmentation and paging

Also Published As

Publication number Publication date
GB2037466A (en) 1980-07-09
JPS5580875A (en) 1980-06-18
DE2947115A1 (en) 1980-06-26
AU538678B2 (en) 1984-08-23
FR2444299A1 (en) 1980-07-11

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