FR2444299A1 - DEVICE FOR SELECTIVELY DELETING AN ANTEMEMORY - Google Patents

DEVICE FOR SELECTIVELY DELETING AN ANTEMEMORY

Info

Publication number
FR2444299A1
FR2444299A1 FR7929801A FR7929801A FR2444299A1 FR 2444299 A1 FR2444299 A1 FR 2444299A1 FR 7929801 A FR7929801 A FR 7929801A FR 7929801 A FR7929801 A FR 7929801A FR 2444299 A1 FR2444299 A1 FR 2444299A1
Authority
FR
France
Prior art keywords
directory
column
memory units
addressable
antememory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7929801A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of FR2444299A1 publication Critical patent/FR2444299A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0822—Copy directories

Abstract

Dispositif pour l'effacement sélectif d'une antémémoire comprenant plusieurs blocs. Le dispositif d'effacement comprend un répertoire principal 32 et un répertoire en double 52 adressables qui comportent plusieurs niveaux et colonnes associatifs; un ensemble d'unités de mémoire 44, 46 adressables, associées chacune à chaque colonne des répertoires; un ensemble d'indicateurs de plein/vide associés à chaque niveau de chaque colonne; des moyens de comptage, des moyens de recherche 54 du répertoire en double pour déterminer si une notification d'écriture correspond à des informations mémorisées dans une des unités de mémoire associée et des moyens 56 pour effacer dans ce cas une entrée dans le répertoire principal. Application aux systèmes de traitement à processeurs multiples.Device for the selective erasure of a cache memory comprising several blocks. The erase device comprises an addressable main directory 32 and a duplicate directory 52 which have several associative levels and columns; a set of addressable memory units 44, 46, each associated with each column of the directories; a set of full / empty indicators associated with each level of each column; counting means, means for searching 54 of the duplicate directory to determine whether a write notification corresponds to information stored in one of the associated memory units and means 56 for in this case deleting an entry in the main directory. Application to processing systems with multiple processors.

FR7929801A 1978-12-11 1979-12-04 DEVICE FOR SELECTIVELY DELETING AN ANTEMEMORY Withdrawn FR2444299A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US96822378A 1978-12-11 1978-12-11

Publications (1)

Publication Number Publication Date
FR2444299A1 true FR2444299A1 (en) 1980-07-11

Family

ID=25513931

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7929801A Withdrawn FR2444299A1 (en) 1978-12-11 1979-12-04 DEVICE FOR SELECTIVELY DELETING AN ANTEMEMORY

Country Status (5)

Country Link
JP (1) JPS5580875A (en)
AU (1) AU538678B2 (en)
DE (1) DE2947115A1 (en)
FR (1) FR2444299A1 (en)
GB (1) GB2037466A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2472232A1 (en) * 1979-12-14 1981-06-26 Honeywell Inf Systems DEVICE AND METHOD FOR DELETING ANEMEMATORY
FR2474721A1 (en) * 1980-01-24 1981-07-31 Honeywell Inf Systems MEMORY DEVICE OF ANTEMEMOIRE
EP0049387A2 (en) * 1980-10-06 1982-04-14 International Business Machines Corporation Multiprocessor system with cache
EP0051745A2 (en) * 1980-11-10 1982-05-19 International Business Machines Corporation Cache storage hierarchy for a multiprocessor system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3138972A1 (en) * 1981-09-30 1983-04-14 Siemens AG, 1000 Berlin und 8000 München ONCHIP MICROPROCESSORCHACHE MEMORY SYSTEM AND METHOD FOR ITS OPERATION

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3723976A (en) * 1972-01-20 1973-03-27 Ibm Memory system with logical and real addressing
US3979726A (en) * 1974-04-10 1976-09-07 Honeywell Information Systems, Inc. Apparatus for selectively clearing a cache store in a processor having segmentation and paging
US4056844A (en) * 1974-02-26 1977-11-01 Hitachi, Ltd. Memory control system using plural buffer address arrays

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3723976A (en) * 1972-01-20 1973-03-27 Ibm Memory system with logical and real addressing
US4056844A (en) * 1974-02-26 1977-11-01 Hitachi, Ltd. Memory control system using plural buffer address arrays
US3979726A (en) * 1974-04-10 1976-09-07 Honeywell Information Systems, Inc. Apparatus for selectively clearing a cache store in a processor having segmentation and paging

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 14, no. 12, mai 1972, pages 3760-3761, New York (USA); *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2472232A1 (en) * 1979-12-14 1981-06-26 Honeywell Inf Systems DEVICE AND METHOD FOR DELETING ANEMEMATORY
FR2474721A1 (en) * 1980-01-24 1981-07-31 Honeywell Inf Systems MEMORY DEVICE OF ANTEMEMOIRE
EP0049387A2 (en) * 1980-10-06 1982-04-14 International Business Machines Corporation Multiprocessor system with cache
EP0049387A3 (en) * 1980-10-06 1984-03-28 International Business Machines Corporation Multiprocessor system with cache
EP0051745A2 (en) * 1980-11-10 1982-05-19 International Business Machines Corporation Cache storage hierarchy for a multiprocessor system
EP0051745A3 (en) * 1980-11-10 1984-07-18 International Business Machines Corporation Cache storage hierarchy for a multiprocessor system

Also Published As

Publication number Publication date
JPS5580875A (en) 1980-06-18
AU538678B2 (en) 1984-08-23
AU5325179A (en) 1980-06-19
GB2037466A (en) 1980-07-09
DE2947115A1 (en) 1980-06-26

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Legal Events

Date Code Title Description
RE Withdrawal of published application