AU5167100A - Behavioral-synthesis electronic design automation tool business-to-business application service provider - Google Patents

Behavioral-synthesis electronic design automation tool business-to-business application service provider

Info

Publication number
AU5167100A
AU5167100A AU51671/00A AU5167100A AU5167100A AU 5167100 A AU5167100 A AU 5167100A AU 51671/00 A AU51671/00 A AU 51671/00A AU 5167100 A AU5167100 A AU 5167100A AU 5167100 A AU5167100 A AU 5167100A
Authority
AU
Australia
Prior art keywords
business
behavioral
service provider
application service
electronic design
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU51671/00A
Other languages
English (en)
Inventor
Bernd Braune
Pradeep Fernandes
Elof Frank
David Knapp
Hans-Joachim Schmidt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Get2Chip
Original Assignee
Get2Chip
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/574,693 external-priority patent/US6470486B1/en
Priority claimed from US09/574,572 external-priority patent/US6516453B1/en
Priority claimed from US09/579,825 external-priority patent/US6782511B1/en
Application filed by Get2Chip filed Critical Get2Chip
Publication of AU5167100A publication Critical patent/AU5167100A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Stored Programmes (AREA)
AU51671/00A 1999-05-26 2000-05-26 Behavioral-synthesis electronic design automation tool business-to-business application service provider Abandoned AU5167100A (en)

Applications Claiming Priority (15)

Application Number Priority Date Filing Date Title
US13612799P 1999-05-26 1999-05-26
US13590299P 1999-05-26 1999-05-26
US13612699P 1999-05-26 1999-05-26
US60135902 1999-05-26
US60136127 1999-05-26
US60136126 1999-05-26
US09574572 2000-05-17
US09574693 2000-05-17
US09/574,693 US6470486B1 (en) 1999-05-26 2000-05-17 Method for delay-optimizing technology mapping of digital logic
US09/574,572 US6516453B1 (en) 1999-05-26 2000-05-17 Method for timing analysis during automatic scheduling of operations in the high-level synthesis of digital systems
US57742600A 2000-05-22 2000-05-22
US09577426 2000-05-22
US09/579,825 US6782511B1 (en) 1999-05-26 2000-05-25 Behavioral-synthesis electronic design automation tool business-to-business application service provider
US09579825 2000-05-25
PCT/US2000/014617 WO2000072185A2 (en) 1999-05-26 2000-05-26 Behavioral-synthesis electronic design automation tool and business-to-business application service provider

Publications (1)

Publication Number Publication Date
AU5167100A true AU5167100A (en) 2000-12-12

Family

ID=27568902

Family Applications (1)

Application Number Title Priority Date Filing Date
AU51671/00A Abandoned AU5167100A (en) 1999-05-26 2000-05-26 Behavioral-synthesis electronic design automation tool business-to-business application service provider

Country Status (5)

Country Link
EP (1) EP1248989A2 (https=)
JP (1) JP4495865B2 (https=)
CN (1) CN1408092A (https=)
AU (1) AU5167100A (https=)
WO (1) WO2000072185A2 (https=)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6961773B2 (en) 2001-01-19 2005-11-01 Esoft, Inc. System and method for managing application service providers
ES2289621T3 (es) * 2001-02-16 2008-02-01 United Parcel Service Of America, Inc. Sistemas que permiten activar y desactivar selectivamente el acceso a aplicaciones de software a traves de una red y sus metodos de uso.
EP1582960B1 (en) * 2001-02-16 2007-07-18 United Parcel Service Of America, Inc. Systems for selectively enabling and disabling access to software applications over a network and method for using same
US7734715B2 (en) * 2001-03-01 2010-06-08 Ricoh Company, Ltd. System, computer program product and method for managing documents
JP2003067453A (ja) * 2001-08-27 2003-03-07 Nec Corp 設計を促進する方法
US10516725B2 (en) 2013-09-26 2019-12-24 Synopsys, Inc. Characterizing target material properties based on properties of similar materials
US9836563B2 (en) 2013-09-26 2017-12-05 Synopsys, Inc. Iterative simulation with DFT and non-DFT
US20160162625A1 (en) 2013-09-26 2016-06-09 Synopsys, Inc. Mapping Intermediate Material Properties To Target Properties To Screen Materials
US10489212B2 (en) 2013-09-26 2019-11-26 Synopsys, Inc. Adaptive parallelization for multi-scale simulation
US10402520B2 (en) 2013-09-26 2019-09-03 Synopsys, Inc. First principles design automation tool
WO2015048400A1 (en) 2013-09-26 2015-04-02 Synopsys, Inc. Estimation of effective channel length for finfets and nano-wires
US10734097B2 (en) 2015-10-30 2020-08-04 Synopsys, Inc. Atomic structure optimization
US10078735B2 (en) 2015-10-30 2018-09-18 Synopsys, Inc. Atomic structure optimization
CN112199918B (zh) * 2020-10-20 2021-09-21 芯和半导体科技(上海)有限公司 一种通用eda模型版图物理连接关系的重建方法
CN113158599B (zh) * 2021-04-14 2023-07-18 广州放芯科技有限公司 基于量子信息学的芯片和芯片化eda装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62202268A (ja) * 1986-02-28 1987-09-05 Nec Corp 回路処理装置
JPS6376065A (ja) * 1986-09-19 1988-04-06 Nec Corp グラフ構造デ−タ表示方式
US5557531A (en) * 1990-04-06 1996-09-17 Lsi Logic Corporation Method and system for creating and validating low level structural description of electronic design from higher level, behavior-oriented description, including estimating power dissipation of physical implementation
US5787010A (en) * 1992-04-02 1998-07-28 Schaefer; Thomas J. Enhanced dynamic programming method for technology mapping of combinational logic circuits
US5544071A (en) * 1993-12-29 1996-08-06 Intel Corporation Critical path prediction for design of circuits
JPH08101861A (ja) * 1994-09-30 1996-04-16 Toshiba Corp 論理回路合成装置
US5535145A (en) * 1995-02-03 1996-07-09 International Business Machines Corporation Delay model abstraction
JP2856141B2 (ja) * 1996-04-01 1999-02-10 日本電気株式会社 遅延情報処理方法及び遅延情報処理装置
GB2325996B (en) * 1997-06-04 2002-06-05 Lsi Logic Corp Distributed computer aided design system and method
JPH11282884A (ja) * 1998-03-30 1999-10-15 Mitsubishi Electric Corp ネットワーク型ｃａｄシステム

Also Published As

Publication number Publication date
JP2003500745A (ja) 2003-01-07
WO2000072185A3 (en) 2001-11-15
CN1408092A (zh) 2003-04-02
JP4495865B2 (ja) 2010-07-07
WO2000072185A2 (en) 2000-11-30
EP1248989A2 (en) 2002-10-16

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase