AU5067390A - Computer system architecture for improved floating point performance - Google Patents

Computer system architecture for improved floating point performance

Info

Publication number
AU5067390A
AU5067390A AU50673/90A AU5067390A AU5067390A AU 5067390 A AU5067390 A AU 5067390A AU 50673/90 A AU50673/90 A AU 50673/90A AU 5067390 A AU5067390 A AU 5067390A AU 5067390 A AU5067390 A AU 5067390A
Authority
AU
Australia
Prior art keywords
computer system
floating point
system architecture
point performance
improved floating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
AU50673/90A
Other versions
AU626117B2 (en
Inventor
Eric Hartwig Jensen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of AU5067390A publication Critical patent/AU5067390A/en
Application granted granted Critical
Publication of AU626117B2 publication Critical patent/AU626117B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU50673/90A 1989-08-31 1990-03-05 Computer system architecture for improved floating point performance Ceased AU626117B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US40102189A 1989-08-31 1989-08-31
US401021 1989-08-31

Publications (2)

Publication Number Publication Date
AU5067390A true AU5067390A (en) 1991-03-07
AU626117B2 AU626117B2 (en) 1992-07-23

Family

ID=23585942

Family Applications (1)

Application Number Title Priority Date Filing Date
AU50673/90A Ceased AU626117B2 (en) 1989-08-31 1990-03-05 Computer system architecture for improved floating point performance

Country Status (3)

Country Link
AU (1) AU626117B2 (en)
GB (1) GB2235554B (en)
HK (1) HK53894A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2256512B (en) * 1991-06-04 1995-03-15 Intel Corp Second level cache controller unit and system
US5649154A (en) * 1992-02-27 1997-07-15 Hewlett-Packard Company Cache memory system having secondary cache integrated with primary cache for use with VLSI circuits
DE4306077A1 (en) * 1992-02-27 1993-09-02 Hewlett Packard Co
US5566324A (en) * 1992-12-24 1996-10-15 Ncr Corporation Computer apparatus including a main memory prefetch cache and method of operation thereof
US6081872A (en) * 1997-07-07 2000-06-27 International Business Machines Corporation Cache reloading performance improvement through the use of early select techniques with and without pipelining

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1301367C (en) * 1988-03-24 1992-05-19 David James Ayers Pseudo set-associative memory cacheing arrangement

Also Published As

Publication number Publication date
GB2235554B (en) 1993-11-17
AU626117B2 (en) 1992-07-23
GB2235554A (en) 1991-03-06
GB9004877D0 (en) 1990-05-02
HK53894A (en) 1994-06-03

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Legal Events

Date Code Title Description
MK14 Patent ceased section 143(a) (annual fees not paid) or expired