GB2235554B - Computer system architecture for improved floating point performance - Google Patents

Computer system architecture for improved floating point performance

Info

Publication number
GB2235554B
GB2235554B GB9004877A GB9004877A GB2235554B GB 2235554 B GB2235554 B GB 2235554B GB 9004877 A GB9004877 A GB 9004877A GB 9004877 A GB9004877 A GB 9004877A GB 2235554 B GB2235554 B GB 2235554B
Authority
GB
United Kingdom
Prior art keywords
computer system
floating point
system architecture
point performance
improved floating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9004877A
Other versions
GB9004877D0 (en
GB2235554A (en
Inventor
Eric Hartwig Jensen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of GB9004877D0 publication Critical patent/GB9004877D0/en
Publication of GB2235554A publication Critical patent/GB2235554A/en
Application granted granted Critical
Publication of GB2235554B publication Critical patent/GB2235554B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
GB9004877A 1989-08-31 1990-03-05 Computer system architecture for improved floating point performance Expired - Fee Related GB2235554B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US40102189A 1989-08-31 1989-08-31

Publications (3)

Publication Number Publication Date
GB9004877D0 GB9004877D0 (en) 1990-05-02
GB2235554A GB2235554A (en) 1991-03-06
GB2235554B true GB2235554B (en) 1993-11-17

Family

ID=23585942

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9004877A Expired - Fee Related GB2235554B (en) 1989-08-31 1990-03-05 Computer system architecture for improved floating point performance

Country Status (3)

Country Link
AU (1) AU626117B2 (en)
GB (1) GB2235554B (en)
HK (1) HK53894A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2256512B (en) * 1991-06-04 1995-03-15 Intel Corp Second level cache controller unit and system
DE4306077A1 (en) * 1992-02-27 1993-09-02 Hewlett Packard Co
US5649154A (en) * 1992-02-27 1997-07-15 Hewlett-Packard Company Cache memory system having secondary cache integrated with primary cache for use with VLSI circuits
US5566324A (en) * 1992-12-24 1996-10-15 Ncr Corporation Computer apparatus including a main memory prefetch cache and method of operation thereof
US6081872A (en) * 1997-07-07 2000-06-27 International Business Machines Corporation Cache reloading performance improvement through the use of early select techniques with and without pipelining

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0334479A2 (en) * 1988-03-24 1989-09-27 Nortel Networks Corporation Pseudo set-associative memory cacheing arrangement

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0334479A2 (en) * 1988-03-24 1989-09-27 Nortel Networks Corporation Pseudo set-associative memory cacheing arrangement

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
CONRAD, DEVLIN, DOBBERPUHL inter alia,"A 50 MIPS (PEAK) 32/646 MICROPROCESSOR" pp76-7,295 *
IEEE INTL. SOLID STATE CIRCUITS CONF. DIGEST TECH. PAPERS 36TH ISSCC, 15-17 FEB 1989,NEW YORK USA; *

Also Published As

Publication number Publication date
AU626117B2 (en) 1992-07-23
GB9004877D0 (en) 1990-05-02
AU5067390A (en) 1991-03-07
HK53894A (en) 1994-06-03
GB2235554A (en) 1991-03-06

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20030305