AU4848700A - Method and apparatus for processor pipeline segmentation and re-assembly - Google Patents
Method and apparatus for processor pipeline segmentation and re-assemblyInfo
- Publication number
- AU4848700A AU4848700A AU48487/00A AU4848700A AU4848700A AU 4848700 A AU4848700 A AU 4848700A AU 48487/00 A AU48487/00 A AU 48487/00A AU 4848700 A AU4848700 A AU 4848700A AU 4848700 A AU4848700 A AU 4848700A
- Authority
- AU
- Australia
- Prior art keywords
- assembly
- processor pipeline
- pipeline segmentation
- segmentation
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 230000011218 segmentation Effects 0.000 title 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Advance Control (AREA)
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13425399P | 1999-05-13 | 1999-05-13 | |
US60134253 | 1999-05-13 | ||
US09/418,663 US6862563B1 (en) | 1998-10-14 | 1999-10-14 | Method and apparatus for managing the configuration and functionality of a semiconductor design |
US09418663 | 1999-10-14 | ||
US52417900A | 2000-03-13 | 2000-03-13 | |
US09524179 | 2000-03-13 | ||
PCT/US2000/013221 WO2000070483A2 (en) | 1999-05-13 | 2000-05-12 | Method and apparatus for processor pipeline segmentation and re-assembly |
Publications (1)
Publication Number | Publication Date |
---|---|
AU4848700A true AU4848700A (en) | 2000-12-05 |
Family
ID=27384547
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU48487/00A Abandoned AU4848700A (en) | 1999-05-13 | 2000-05-12 | Method and apparatus for processor pipeline segmentation and re-assembly |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1190337A2 (en) |
CN (1) | CN1217261C (en) |
AU (1) | AU4848700A (en) |
TW (1) | TW589544B (en) |
WO (1) | WO2000070483A2 (en) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6862563B1 (en) | 1998-10-14 | 2005-03-01 | Arc International | Method and apparatus for managing the configuration and functionality of a semiconductor design |
US6988154B2 (en) | 2000-03-10 | 2006-01-17 | Arc International | Memory interface and method of interfacing between functional entities |
US7000095B2 (en) | 2002-09-06 | 2006-02-14 | Mips Technologies, Inc. | Method and apparatus for clearing hazards using jump instructions |
CN100451951C (en) * | 2006-01-26 | 2009-01-14 | 深圳艾科创新微电子有限公司 | 5+3 levels pipeline structure and method in RISC CPU |
US8127113B1 (en) | 2006-12-01 | 2012-02-28 | Synopsys, Inc. | Generating hardware accelerators and processor offloads |
JP5395383B2 (en) * | 2008-08-21 | 2014-01-22 | 株式会社東芝 | Control system with pipeline arithmetic processor |
CN102194350B (en) * | 2011-03-24 | 2013-01-30 | 大连理工大学 | VHDL (Very-High-Speed Integrated Circuit Hardware Description Language)-based CPU (Central Processing Unit) |
CN102830953B (en) * | 2012-08-02 | 2017-08-25 | 中兴通讯股份有限公司 | Command processing method and network processing unit instruction processing unit |
CN104793987B (en) * | 2014-01-17 | 2018-08-03 | 中国移动通信集团公司 | A kind of data processing method and device |
US9971516B2 (en) | 2016-10-17 | 2018-05-15 | International Business Machines Corporation | Load stall interrupt |
CN111399912B (en) * | 2020-03-26 | 2022-11-22 | 超睿科技(长沙)有限公司 | Instruction scheduling method, system and medium for multi-cycle instruction |
CN113961247B (en) * | 2021-09-24 | 2022-10-11 | 北京睿芯众核科技有限公司 | RISC-V processor based vector access/fetch instruction execution method, system and device |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5019967A (en) * | 1988-07-20 | 1991-05-28 | Digital Equipment Corporation | Pipeline bubble compression in a computer system |
DE69130519T2 (en) * | 1990-06-29 | 1999-06-10 | Digital Equipment Corp., Maynard, Mass. | High-performance multiprocessor with floating point unit and method for its operation |
EP0649085B1 (en) * | 1993-10-18 | 1998-03-04 | Cyrix Corporation | Microprocessor pipe control and register translation |
-
2000
- 2000-05-12 WO PCT/US2000/013221 patent/WO2000070483A2/en active Application Filing
- 2000-05-12 EP EP00930715A patent/EP1190337A2/en not_active Withdrawn
- 2000-05-12 AU AU48487/00A patent/AU4848700A/en not_active Abandoned
- 2000-05-12 CN CN008084580A patent/CN1217261C/en not_active Expired - Fee Related
- 2000-07-05 TW TW089109198A patent/TW589544B/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN1217261C (en) | 2005-08-31 |
EP1190337A2 (en) | 2002-03-27 |
WO2000070483A3 (en) | 2001-08-09 |
CN1355900A (en) | 2002-06-26 |
TW589544B (en) | 2004-06-01 |
WO2000070483A2 (en) | 2000-11-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK6 | Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase |