AU4825897A - High tolerance cavities in chip packages - Google Patents

High tolerance cavities in chip packages

Info

Publication number
AU4825897A
AU4825897A AU48258/97A AU4825897A AU4825897A AU 4825897 A AU4825897 A AU 4825897A AU 48258/97 A AU48258/97 A AU 48258/97A AU 4825897 A AU4825897 A AU 4825897A AU 4825897 A AU4825897 A AU 4825897A
Authority
AU
Australia
Prior art keywords
cavities
chip packages
high tolerance
tolerance
packages
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU48258/97A
Other languages
English (en)
Inventor
Boydd Piper
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
WL Gore and Associates Inc
Original Assignee
WL Gore and Associates Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by WL Gore and Associates Inc filed Critical WL Gore and Associates Inc
Publication of AU4825897A publication Critical patent/AU4825897A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4878—Mechanical treatment, e.g. deforming
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/4801—Structure
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    • H01L2224/481—Disposition
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    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Adhesives Or Adhesive Processes (AREA)
AU48258/97A 1996-11-08 1997-10-22 High tolerance cavities in chip packages Abandoned AU4825897A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US74597196A 1996-11-08 1996-11-08
US08745971 1996-11-08
PCT/US1997/019024 WO1998020546A1 (fr) 1996-11-08 1997-10-22 Cavites a haute tolerance dans des boitiers de puces

Publications (1)

Publication Number Publication Date
AU4825897A true AU4825897A (en) 1998-05-29

Family

ID=24999003

Family Applications (1)

Application Number Title Priority Date Filing Date
AU48258/97A Abandoned AU4825897A (en) 1996-11-08 1997-10-22 High tolerance cavities in chip packages

Country Status (2)

Country Link
AU (1) AU4825897A (fr)
WO (1) WO1998020546A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2962578B1 (fr) * 2010-07-09 2012-08-03 E2V Semiconductors Composant électronique en boitier céramique
CN105246377A (zh) 2013-05-22 2016-01-13 伊欧维新有限责任公司 基于塑料制造的物品和形成工艺

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3728469A (en) * 1971-03-11 1973-04-17 Owens Illinois Inc Cavity structure
WO1991000618A1 (fr) * 1989-07-03 1991-01-10 General Electric Company Systemes electroniques disposes dans un environnement soumis a des efforts importants
US5205032A (en) * 1990-09-28 1993-04-27 Kabushiki Kaisha Toshiba Electronic parts mounting apparatus
JP2653554B2 (ja) * 1990-12-11 1997-09-17 シャープ株式会社 テープキャリア半導体素子の製造方法
GB2292003A (en) * 1994-07-29 1996-02-07 Ibm Uk Direct chip attach
JP3163912B2 (ja) * 1994-09-06 2001-05-08 日立電線株式会社 Ｂｇａパッケージ

Also Published As

Publication number Publication date
WO1998020546A1 (fr) 1998-05-14

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