AU4427085A - Process for superposing two photoresist layers - Google Patents

Process for superposing two photoresist layers

Info

Publication number
AU4427085A
AU4427085A AU44270/85A AU4427085A AU4427085A AU 4427085 A AU4427085 A AU 4427085A AU 44270/85 A AU44270/85 A AU 44270/85A AU 4427085 A AU4427085 A AU 4427085A AU 4427085 A AU4427085 A AU 4427085A
Authority
AU
Australia
Prior art keywords
superposing
photoresist layers
photoresist
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
AU44270/85A
Other versions
AU579161B2 (en
Inventor
Rudy Eddy Horre
Dirk Marice Veernaert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent NV
Original Assignee
International Standard Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Standard Electric Corp filed Critical International Standard Electric Corp
Publication of AU4427085A publication Critical patent/AU4427085A/en
Application granted granted Critical
Publication of AU579161B2 publication Critical patent/AU579161B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Materials For Photolithography (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Formation Of Insulating Films (AREA)
AU44270/85A 1984-07-13 1985-06-28 Process for superposing two photoresist layers Expired - Fee Related AU579161B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
BE900156 1984-07-13
BE2/60459A BE900156A (en) 1984-07-13 1984-07-13 PROCESS FOR SUPERIMPOSING TWO LAYERS OF POSITIVE PHOTOSENSITIVE VARNISH.

Publications (2)

Publication Number Publication Date
AU4427085A true AU4427085A (en) 1986-01-16
AU579161B2 AU579161B2 (en) 1988-11-17

Family

ID=3865700

Family Applications (1)

Application Number Title Priority Date Filing Date
AU44270/85A Expired - Fee Related AU579161B2 (en) 1984-07-13 1985-06-28 Process for superposing two photoresist layers

Country Status (4)

Country Link
EP (1) EP0171111A3 (en)
JP (1) JPS6151923A (en)
AU (1) AU579161B2 (en)
BE (1) BE900156A (en)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4767721A (en) * 1986-02-10 1988-08-30 Hughes Aircraft Company Double layer photoresist process for well self-align and ion implantation masking
US5372914A (en) * 1992-03-24 1994-12-13 Kabushiki Kaisha Toshiba Pattern forming method
US8852851B2 (en) 2006-07-10 2014-10-07 Micron Technology, Inc. Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
US7989307B2 (en) 2008-05-05 2011-08-02 Micron Technology, Inc. Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same
US10151981B2 (en) 2008-05-22 2018-12-11 Micron Technology, Inc. Methods of forming structures supported by semiconductor substrates
US8409457B2 (en) 2008-08-29 2013-04-02 Micron Technology, Inc. Methods of forming a photoresist-comprising pattern on a substrate
US8039399B2 (en) 2008-10-09 2011-10-18 Micron Technology, Inc. Methods of forming patterns utilizing lithography and spacers
US8247302B2 (en) 2008-12-04 2012-08-21 Micron Technology, Inc. Methods of fabricating substrates
US8796155B2 (en) 2008-12-04 2014-08-05 Micron Technology, Inc. Methods of fabricating substrates
US8273634B2 (en) 2008-12-04 2012-09-25 Micron Technology, Inc. Methods of fabricating substrates
US8268543B2 (en) 2009-03-23 2012-09-18 Micron Technology, Inc. Methods of forming patterns on substrates
US9330934B2 (en) 2009-05-18 2016-05-03 Micron Technology, Inc. Methods of forming patterns on substrates
US8518788B2 (en) 2010-08-11 2013-08-27 Micron Technology, Inc. Methods of forming a plurality of capacitors
US8455341B2 (en) 2010-09-02 2013-06-04 Micron Technology, Inc. Methods of forming features of integrated circuitry
US8575032B2 (en) 2011-05-05 2013-11-05 Micron Technology, Inc. Methods of forming a pattern on a substrate
US9076680B2 (en) 2011-10-18 2015-07-07 Micron Technology, Inc. Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array
US9177794B2 (en) 2012-01-13 2015-11-03 Micron Technology, Inc. Methods of patterning substrates
US8629048B1 (en) 2012-07-06 2014-01-14 Micron Technology, Inc. Methods of forming a pattern on a substrate

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3131031A1 (en) * 1981-08-05 1983-02-24 Siemens AG, 1000 Berlin und 8000 München Method for producing area doping when fabricating integrated complementary MOS field effect transistors
DE3588185T2 (en) * 1984-08-13 1998-12-17 Hyundai Electronics America, Milpitas, Calif. Process for the production of patterned photo protective lacquer layers

Also Published As

Publication number Publication date
EP0171111A3 (en) 1987-07-22
AU579161B2 (en) 1988-11-17
EP0171111A2 (en) 1986-02-12
JPS6151923A (en) 1986-03-14
BE900156A (en) 1985-01-14

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