AU3762093A - Parallel vector processor architecture - Google Patents
Parallel vector processor architectureInfo
- Publication number
- AU3762093A AU3762093A AU37620/93A AU3762093A AU3762093A AU 3762093 A AU3762093 A AU 3762093A AU 37620/93 A AU37620/93 A AU 37620/93A AU 3762093 A AU3762093 A AU 3762093A AU 3762093 A AU3762093 A AU 3762093A
- Authority
- AU
- Australia
- Prior art keywords
- processor architecture
- vector processor
- parallel vector
- parallel
- architecture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
- G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
- F02B—INTERNAL-COMBUSTION PISTON ENGINES; COMBUSTION ENGINES IN GENERAL
- F02B75/00—Other engines
- F02B75/02—Engines characterised by their cycles, e.g. six-stroke
- F02B2075/022—Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle
- F02B2075/027—Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle four
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9206126 | 1992-03-20 | ||
GB929206126A GB9206126D0 (en) | 1992-03-20 | 1992-03-20 | Parallel vector processor architecture |
Publications (1)
Publication Number | Publication Date |
---|---|
AU3762093A true AU3762093A (en) | 1993-10-21 |
Family
ID=10712538
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU37620/93A Abandoned AU3762093A (en) | 1992-03-20 | 1993-03-22 | Parallel vector processor architecture |
Country Status (3)
Country | Link |
---|---|
AU (1) | AU3762093A (en) |
GB (1) | GB9206126D0 (en) |
WO (1) | WO1993019431A1 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
RU2045095C1 (en) * | 1994-09-14 | 1995-09-27 | Виталий Оскарович Гроппен | Process of optimum formation of visible image |
US5768445A (en) * | 1996-09-13 | 1998-06-16 | Silicon Graphics, Inc. | Compression and decompression scheme performed on shared workstation memory by media coprocessor |
EP1126409A4 (en) * | 1999-05-10 | 2003-09-10 | Sony Corp | Image processing apparatus, robot apparatus and image processing method |
US6460120B1 (en) * | 1999-08-27 | 2002-10-01 | International Business Machines Corporation | Network processor, memory organization and methods |
FR3011659B1 (en) * | 2013-10-04 | 2015-10-16 | Commissariat Energie Atomique | ELECTRONIC CIRCUIT, PARTICULARLY ABLE TO IMPLEMENTATION OF A NETWORK OF NEURONS, AND NEURONAL SYSTEM |
CN106485322B (en) * | 2015-10-08 | 2019-02-26 | 上海兆芯集成电路有限公司 | It is performed simultaneously the neural network unit of shot and long term memory cell calculating |
CN105468335B (en) * | 2015-11-24 | 2017-04-12 | 中国科学院计算技术研究所 | Pipeline-level operation device, data processing method and network-on-chip chip |
US11263011B2 (en) | 2018-11-28 | 2022-03-01 | International Business Machines Corporation | Compound instruction set architecture for a neural inference chip |
CN113342721B (en) * | 2021-07-06 | 2022-09-23 | 无锡众星微系统技术有限公司 | DMA design method for memory controller |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5163133A (en) * | 1987-02-17 | 1992-11-10 | Sam Technology, Inc. | Parallel processing system having a broadcast, result, and instruction bus for transmitting, receiving and controlling the computation of data |
WO1991019259A1 (en) * | 1990-05-30 | 1991-12-12 | Adaptive Solutions, Inc. | Distributive, digital maximization function architecture and method |
FR2666670B1 (en) * | 1990-09-11 | 1994-07-01 | Lawson Jean Christophe | PARALLEL CALCULATION CO-OPTIMIZER OPTIMIZED FOR TREATMENTS BASED ON HOLLOW MATRICES. |
-
1992
- 1992-03-20 GB GB929206126A patent/GB9206126D0/en active Pending
-
1993
- 1993-03-22 AU AU37620/93A patent/AU3762093A/en not_active Abandoned
- 1993-03-22 WO PCT/GB1993/000580 patent/WO1993019431A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO1993019431A1 (en) | 1993-09-30 |
GB9206126D0 (en) | 1992-05-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
AU4804493A (en) | Massively parallel computer including auxiliary vector processor | |
AU5099593A (en) | Improved vector quantization | |
AU8097291A (en) | Surround processor | |
AU4166393A (en) | Auto-reclosers | |
AU3561193A (en) | TNF-muteins | |
AU3991693A (en) | Pyrazinoindoles | |
AU3591693A (en) | Grain processor | |
AU3686793A (en) | Thermo-actuator | |
AU4177593A (en) | Benzophenonehydrazones | |
AU3042892A (en) | Rockbolt | |
AU1751392A (en) | Mammalian expression vector | |
AU659324B2 (en) | Banknote processor | |
GB9311935D0 (en) | Processor | |
AU3762093A (en) | Parallel vector processor architecture | |
AU4156393A (en) | Heterocyclyltriazolinones | |
AU5795094A (en) | Image processor | |
AU3562193A (en) | Morpholin- and thiomorpholin-4-ylamides | |
AU3461693A (en) | Saddle-cloth | |
AU4164793A (en) | Heterocyclyltriazolinones | |
AU4632493A (en) | Weathershed | |
EP0620533A3 (en) | Vector processor. | |
GB9303850D0 (en) | Vector | |
AU7192594A (en) | Drying enclosure | |
GB9324195D0 (en) | Beams processor | |
AU4864693A (en) | Alkoxymethyl-substituted pyridonebiphenyls |