AU3762093A - Parallel vector processor architecture - Google Patents

Parallel vector processor architecture

Info

Publication number
AU3762093A
AU3762093A AU37620/93A AU3762093A AU3762093A AU 3762093 A AU3762093 A AU 3762093A AU 37620/93 A AU37620/93 A AU 37620/93A AU 3762093 A AU3762093 A AU 3762093A AU 3762093 A AU3762093 A AU 3762093A
Authority
AU
Australia
Prior art keywords
processor architecture
vector processor
parallel vector
parallel
architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU37620/93A
Inventor
Stuart Mackay
Stuart Mackie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MAXYS CIRCUIT TECHNOLOGY Ltd
Original Assignee
MAXYS CIRCUIT TECH Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MAXYS CIRCUIT TECH Ltd filed Critical MAXYS CIRCUIT TECH Ltd
Publication of AU3762093A publication Critical patent/AU3762093A/en
Abandoned legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015One dimensional arrays, e.g. rings, linear arrays, buses
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858Result writeback, i.e. updating the architectural state or memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/20Processor architectures; Processor configuration, e.g. pipelining
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F02COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
    • F02BINTERNAL-COMBUSTION PISTON ENGINES; COMBUSTION ENGINES IN GENERAL
    • F02B75/00Other engines
    • F02B75/02Engines characterised by their cycles, e.g. six-stroke
    • F02B2075/022Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle
    • F02B2075/027Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle four

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
AU37620/93A 1992-03-20 1993-03-22 Parallel vector processor architecture Abandoned AU3762093A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9206126 1992-03-20
GB929206126A GB9206126D0 (en) 1992-03-20 1992-03-20 Parallel vector processor architecture

Publications (1)

Publication Number Publication Date
AU3762093A true AU3762093A (en) 1993-10-21

Family

ID=10712538

Family Applications (1)

Application Number Title Priority Date Filing Date
AU37620/93A Abandoned AU3762093A (en) 1992-03-20 1993-03-22 Parallel vector processor architecture

Country Status (3)

Country Link
AU (1) AU3762093A (en)
GB (1) GB9206126D0 (en)
WO (1) WO1993019431A1 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2045095C1 (en) * 1994-09-14 1995-09-27 Виталий Оскарович Гроппен Process of optimum formation of visible image
US5768445A (en) * 1996-09-13 1998-06-16 Silicon Graphics, Inc. Compression and decompression scheme performed on shared workstation memory by media coprocessor
EP1126409A4 (en) * 1999-05-10 2003-09-10 Sony Corp Image processing apparatus, robot apparatus and image processing method
US6460120B1 (en) * 1999-08-27 2002-10-01 International Business Machines Corporation Network processor, memory organization and methods
FR3011659B1 (en) * 2013-10-04 2015-10-16 Commissariat Energie Atomique ELECTRONIC CIRCUIT, PARTICULARLY ABLE TO IMPLEMENTATION OF A NETWORK OF NEURONS, AND NEURONAL SYSTEM
CN106485322B (en) * 2015-10-08 2019-02-26 上海兆芯集成电路有限公司 It is performed simultaneously the neural network unit of shot and long term memory cell calculating
CN105468335B (en) * 2015-11-24 2017-04-12 中国科学院计算技术研究所 Pipeline-level operation device, data processing method and network-on-chip chip
US11263011B2 (en) 2018-11-28 2022-03-01 International Business Machines Corporation Compound instruction set architecture for a neural inference chip
CN113342721B (en) * 2021-07-06 2022-09-23 无锡众星微系统技术有限公司 DMA design method for memory controller

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5163133A (en) * 1987-02-17 1992-11-10 Sam Technology, Inc. Parallel processing system having a broadcast, result, and instruction bus for transmitting, receiving and controlling the computation of data
WO1991019259A1 (en) * 1990-05-30 1991-12-12 Adaptive Solutions, Inc. Distributive, digital maximization function architecture and method
FR2666670B1 (en) * 1990-09-11 1994-07-01 Lawson Jean Christophe PARALLEL CALCULATION CO-OPTIMIZER OPTIMIZED FOR TREATMENTS BASED ON HOLLOW MATRICES.

Also Published As

Publication number Publication date
WO1993019431A1 (en) 1993-09-30
GB9206126D0 (en) 1992-05-06

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