AU3698599A - Speed-optimized cache system - Google Patents

Speed-optimized cache system

Info

Publication number
AU3698599A
AU3698599A AU36985/99A AU3698599A AU3698599A AU 3698599 A AU3698599 A AU 3698599A AU 36985/99 A AU36985/99 A AU 36985/99A AU 3698599 A AU3698599 A AU 3698599A AU 3698599 A AU3698599 A AU 3698599A
Authority
AU
Australia
Prior art keywords
speed
cache system
optimized cache
optimized
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
AU36985/99A
Other languages
English (en)
Inventor
Robert Munch
Martin Vorbach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pact Informationstechnologie GmbH
Original Assignee
Pact Informationstechnologie GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pact Informationstechnologie GmbH filed Critical Pact Informationstechnologie GmbH
Publication of AU3698599A publication Critical patent/AU3698599A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851—Cache with interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/109—Address translation for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU36985/99A 1998-03-06 1999-03-07 Speed-optimized cache system Withdrawn AU3698599A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19809640 1998-03-06
DE19809640A DE19809640A1 (de) 1998-03-06 1998-03-06 Geschwindigkeitsoptimiertes Cachesystem
PCT/DE1999/000639 WO1999045474A2 (de) 1998-03-06 1999-03-07 Geschwindigkeitsoptimiertes cachesystem

Publications (1)

Publication Number Publication Date
AU3698599A true AU3698599A (en) 1999-09-20

Family

ID=7859951

Family Applications (1)

Application Number Title Priority Date Filing Date
AU36985/99A Withdrawn AU3698599A (en) 1998-03-06 1999-03-07 Speed-optimized cache system

Country Status (3)

Country Link
AU (1) AU3698599A (de)
DE (2) DE19809640A1 (de)
WO (1) WO1999045474A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6606684B1 (en) 2000-03-31 2003-08-12 Intel Corporation Multi-tiered memory bank having different data buffer sizes with a programmable bank select
EP1514193B1 (de) 2002-02-18 2008-07-23 PACT XPP Technologies AG Bussysteme und rekonfigurationsverfahren
MY139705A (en) * 2004-07-19 2009-10-30 Basf Ag Mixtures of hyperbranched polyesters with polycarbonates as additive for polyester molding compositions

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07502358A (ja) * 1991-12-23 1995-03-09 インテル・コーポレーション マイクロプロセッサーのクロックに依るマルチプル・アクセスのためのインターリーブ・キャッシュ
US5581734A (en) * 1993-08-02 1996-12-03 International Business Machines Corporation Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity
JP2000501539A (ja) * 1996-09-25 2000-02-08 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ アドレス競合検出を持つ多重ポート・キャッシュメモリ

Also Published As

Publication number Publication date
WO1999045474A3 (de) 1999-11-11
DE19980350D2 (de) 2001-03-29
DE19809640A1 (de) 1999-09-09
WO1999045474A2 (de) 1999-09-10

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