AU3124384A - Bit rate transformation of digital signals - Google Patents
Bit rate transformation of digital signalsInfo
- Publication number
- AU3124384A AU3124384A AU31243/84A AU3124384A AU3124384A AU 3124384 A AU3124384 A AU 3124384A AU 31243/84 A AU31243/84 A AU 31243/84A AU 3124384 A AU3124384 A AU 3124384A AU 3124384 A AU3124384 A AU 3124384A
- Authority
- AU
- Australia
- Prior art keywords
- pulse
- clock pulse
- digital signals
- clock
- bit rate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/12—Arrangements providing for calling or supervisory signals
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Time-Division Multiplex Systems (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention consists of a method for bitrate transformation of digital signals in digital transmission systems in which additional bits are inserted in the digital signal before transmission at the transmitter and then removed again at the receiver. For this purpose a clock pulse is to be generated for writing into and reading out from a memory with address counters, and there must be no systematic pulse jitter. For this purpose the invention provides that on the transmitter side, the clock oscillator for the read-out pulse is phase-locked to a value m/n times the frequency of the clock pulse for writing into the relevant address counter. On the receiver side, the clock oscillator for the read-out clock pulse is phase-locked to a value n/m times the frequency of the write clock pulse. <IMAGE>
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE3327380 | 1983-07-29 | ||
DE19833327380 DE3327380A1 (en) | 1983-07-29 | 1983-07-29 | METHOD FOR BITRATE TRANSFORMING DIGITAL SIGNALS |
Publications (2)
Publication Number | Publication Date |
---|---|
AU3124384A true AU3124384A (en) | 1985-01-31 |
AU572533B2 AU572533B2 (en) | 1988-05-12 |
Family
ID=6205229
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU31243/84A Ceased AU572533B2 (en) | 1983-07-29 | 1984-07-27 | Bit rate transformation of digital signals |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0133279B1 (en) |
AT (1) | ATE63024T1 (en) |
AU (1) | AU572533B2 (en) |
DE (2) | DE3327380A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5132970A (en) * | 1989-07-12 | 1992-07-21 | U.S. Philips Corporation | Bit rate adaptation circuit arrangement comprising a justification decision circuit |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63166330A (en) * | 1986-12-19 | 1988-07-09 | ジーメンス・アクチエンゲゼルシヤフト | Method and apparatus for digital signal with low bit transmission speed in time-slot of time-sharing multiplex signal provided for high bit rate transmission speed |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2006504C3 (en) * | 1970-02-13 | 1979-02-01 | Allgemeine Elektricitaets-Gesellschaft Aeg-Telefunken, 6000 Frankfurt | Method for inserting an equidistant sequence of binary signals into the pulse frame of a transmission link |
CH621445A5 (en) * | 1976-09-09 | 1981-01-30 | Gretag Ag | |
IT1074199B (en) * | 1976-12-23 | 1985-04-17 | Italiana Telecomunicazioni Ora | ELASTIC MEMORY FOR THE SUPPRESSION OF PHASE DISORDER (JITTER) IN TRANSMISSION SYSTEMS FOR DIGITAL SIGNALS |
JPS5923660B2 (en) * | 1979-02-19 | 1984-06-04 | 株式会社日立製作所 | Digital signal transmission method |
DE2922338C2 (en) * | 1979-06-01 | 1982-10-07 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Line termination device for broadband transmission links |
JPS5859641A (en) * | 1981-10-05 | 1983-04-08 | Nec Corp | Digital transmitting device |
PT77084B (en) * | 1982-07-23 | 1986-01-27 | British Telecomm | Improvements relating to data transmission |
-
1983
- 1983-07-29 DE DE19833327380 patent/DE3327380A1/en not_active Withdrawn
-
1984
- 1984-07-24 EP EP84108753A patent/EP0133279B1/en not_active Expired - Lifetime
- 1984-07-24 AT AT84108753T patent/ATE63024T1/en not_active IP Right Cessation
- 1984-07-24 DE DE8484108753T patent/DE3484489D1/en not_active Expired - Fee Related
- 1984-07-27 AU AU31243/84A patent/AU572533B2/en not_active Ceased
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5132970A (en) * | 1989-07-12 | 1992-07-21 | U.S. Philips Corporation | Bit rate adaptation circuit arrangement comprising a justification decision circuit |
Also Published As
Publication number | Publication date |
---|---|
EP0133279B1 (en) | 1991-04-24 |
EP0133279A2 (en) | 1985-02-20 |
ATE63024T1 (en) | 1991-05-15 |
EP0133279A3 (en) | 1987-10-07 |
DE3327380A1 (en) | 1985-02-07 |
AU572533B2 (en) | 1988-05-12 |
DE3484489D1 (en) | 1991-05-29 |
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