AU2765502A - Architecture for an ATM subscriber access multiplexer - Google Patents

Description

P/00/0o11 Regulation 3.2

AUSTRALIA

Patents Act 1990

ORIGINAL

COMPLETE SPECIFICATION DIVISIONAL PATENT Invention Title: Architecture for an ATM subscriber access multiplexer system The following statement is a full description of this invention, including the best method of performing it known to us: 004061512v7.doc 1 Architecture For An ATM Subscriber Access Multiplexer System This invention relates to providing high-speed communications services to ordinary residences and small businesses on digital subscriber lines.

The sudden emergence of the Internet has produced an urgent demand for high-speed communications services to ordinary residences and small businesses. These services are distinguished by bursty data patterns and asymmetrical data transfer far more information sent toward the subscriber premises than received from it. A partial response to this need, at least on the physical signal level, has been found in new llxDSLII transmission technologies, such as ADS (Asymmetric Digital Subscriber Line). These have recently become sophisticated enough to allow dynamic bit-rate adaptation on each subscriber line, so that a wide range of loop lengths can be accommodated. But all this variability (bursty data, dynamic bit rates, etc.) has made it nearly 0 impossible to predict, control, manage, or guarantee the Quality of Service (QoS) provided to each subscriber, as required for a viable commercial service.

0.

Several companies are working on ADS products using DMT (Discrete Multi-Tone) 15 and/or CAP (Carrier-less Amplitude Phase Modulation) technology each with their own o ee o* equipment configurations and target applications. These products simply multiplex the ADS data streams together with little or no flexible bandwidth control and no QoS management features.

V,.0e.

0 The applicant does not concede that the prior art discussed herein forms part of the common general knowledge in the art, in Australia, at the priority date of the present application.

o. 20 According to a first aspect of the present invention there is provided a network termination equipment for use in a shelf of a telecommunications system, said network termination equipment for connection to an asynchronous transfer mode (ATM) network and to a plurality of line termination equipment also for use in said shelf for connection to subscriber equipment, said network termination equipment including: physical medium termination equipment for interfacing to a physical medium by means of a serial input/output connection to said ATM network for providing a parallel input/output; transmission conveyance means connected to said parallel input/output for recovering/mapping ATM cells from/to frames of a transport format of said serial input/output; ATM layer processing means connected to said transmission conveyance means for layer processing downstream ATM cells recovered by said transmission conveyance means and for providing upstream ATM cells to said transmission conveyance means; and an ATM bus interface responsive to downstream ATM cells from said ATM layer 004061512v7.doc 2 processing means for providing said downstream ATM cells with a guard byte for an ATM bus in said shelf and responsive to upstream ATM cells with a guard byte for providing said upstream cells to said ATM layer processing means without said guard byte.

According to a second aspect of the present invention there is provided a network termination equipment, for connection to an asynchronous transfer mode (ATM) network, said network termination equipment including: physical medium termination equipment for interfacing to a physical medium by means of a serial input/output connection to said ATM network for providing a parallel input/output; transmission conveyance means connected to said parallel input/output for recovering/mapping ATM cells from/to frames of a transport format of said serial input/output; ATM layer processing means connected to said transmission conveyance means for layer processing downstream ATM cells recovered by said transmission conveyance means and for providing upstream ATM cells to said transmission conveyance means; and an ATM bus interface responsive to downstream ATM cells from said ATM layer S :15 processing means for providing said downstream ATM cells with a guard byte for an ATM bus in said shelf and responsive to upstream ATM cells with a guard byte for providing said upstream cells to said ATM layer processing means without said guard byte.

According to a third aspect of the present invention there is provided a network termination equipment for use in a shelf of a telecommunication system, said network termination 20 equipment for connection to an asynchronous transfer mode (ATM) network, said network termination equipment including: physical medium termination equipment for interfacing to a physical medium by means of a serial input/output connection to said ATM network for providing a parallel input/output; transmission conveyance means connected to said parallel input/output for recovering/mapping ATM cells from/to frames of a transport format of said serial input/output; ATM layer processing means connected to said transmission conveyance means for layer processing downstream ATM cells recovered by said transmission conveyance means and for providing upstream ATM cells to said transmission conveyance means; and an ATM bus interface responsive to downstream ATM cells from said ATM layer processing means for providing said downstream ATM cells with a guard byte for an ATM bus in said shelf and responsive to upstream ATM cells with a guard byte for providing said upstream cells to said ATM layer processing means without said guard byte.

004061512v7.doc 3 In the preferred embodiments said physical medium termination equipment includes an optical interface.

Preferably said physical medium termination equipment includes means for locking onto a received downstream clock signal and means for providing a transmit clock in an upstream direction.

It is also preferable that said transmission conveyance means includes frame alignment recovery means for use in a downstream direction and frame generation means for use in an upstream direction. The transmission conveyance means preferably includes descrambling/scrambling means for descrambling/scrambling STM1/STS3c signals.

In the preferred embodiment the ATM layer processing means includes ATM cell S extraction/insertion means, ATM cell header error control checking and ATM layer processing plus cell rate decoupling.

Configurations of the architecture are taught for equipment located in local Central Offices, Remote sites and at customers' premises, as appropriate for a variety of cable plant 15 topologies. The system building blocks (boards, connectors, shields, etc.) are physically organised in a new shelf arrangement detailed below that packs all these features into a high-density shelf that can be installed easily in conventional central offices, and remote cabinets and vaults.

Thus, the present invention provides a high-speed digital access communications system, covering a wide range of configurations and applications, using new packet and XDSL 20 technologies with the possibility to offer subscribers the variety of QoS classes defined, for example, in the various ATM Forum specifications. Since it uses the existing copper cable plant already deployed throughout the developed world, the system is economical allowing Local Exchange Carriers to compete with alternative service providers such as CATV companies (which are deploying heavily overbooked cable modem technology on their coax cable plant). The system also preserves the reliability and simplicity of analog "lifeline" POTS, so that subscribers and telephone operating companies are not required to change the way voice services are provided.

These and other features and advantages of the present invention will become more apparent in light of the following detailed description of an exemplary embodiment thereof, as illustrated in the accompanying drawing, in which: Figure 1 illustrates a basic XDSL shelf layout, which may be an ADS shelf in the embodiment illustrated, for use, for example, in an ATM subscriber access multiplexer (ASAM) 004061512v7.doc 4 system, according to the present invention.

Figure 1A shows the shelf of Figure 1 in detail, and in particular shows how front access is achieved.

Figure 1B shows a standard configuration of XDSL shelves in a Central Office (CO) rack, according to the present invention.

Figure 1C shows a shelf without cards, with various connectors for connection to the backplane, a terminal block, etc.

Figure 1D shows a side view of a shelf, according to the present invention.

Figure 1E shows a rack, according to the present invention, for housing a selected number of shelves, according to the present invention.

Figure 2 shows a functional block diagram of the present invention whereby high speed packetized data in, eg., ATM format is combined with traditional POTS service, eg., in an XDSL shelf which may be an ADS shelf in the embodiment illustrated for providing the means whereby S POTS lifeline services on a twisted copper pair are overlaid with high speed digital services for 15 communicating high bandwidth services to a customer's premises.

S; Figure 3 shows further details of the XDSL shelf of Figure 2 which can be an ADS shelf, as illustrated, for serving a plurality of customer premises, in this case with up to 48 lines.

Figure 3A illustrates a bus access method for prioritized data wherein guaranteed bandwidth and overbooking in a same QoS class is mixed with a fairness feature, according to 20 the present invention.

Figure 4 shows additional flexibility built into an XDSL shelf which is shown here in two different embodiments, one called a "hub" and the other a "remote", for use in an ASAM system, according to the present invention.

Figure 4A shows LT-LPF BPA wiring and LT-BPA transceivers for supporting the "hub" applications with DS-3 links to "remote" shelves, according to the present invention.

Figure 4B shows wiring with non-redundant DS-3 LT card installed for the "hub" application, according to the present invention.

Figure 4C shows redundant DS-3 LTs on the same shelf in a "hub" application, according to the present invention.

Figure 4D shows switch signal wiring for redundant DS3 LTs in the same shelf for a "hub" application, according to the present invention.

Figure 4E shows a solution for DS-3 LT card redundancy in separate shelves for a "hub" 004061512v7.doc application, so as to provide IQ bus redundancy, according to the present invention, where only a single IQ bus is provided per shelf.

Figure 5 shows how the hub and remotes of Figure 4 could be deployed in one embodiment of an ASAM system, according to the present invention.

Figure 6 shows four XDSL shelves in one rack of an ASAM system; the shelves may be ADS shelves as illustrated, for use with redundant IQ bus extender cards (EXT) in an bank switchover scheme to extend the IQ bus to additional shelves to serve, eg., with three such racks, up to 576 subscribers.

Figure 7A shows a schematic block diagram of a lowpass filter card for insertion in one of the slots 24 in the upper section 22 of the shelf 10 of Figure 1.

Figure 7B shows a side view of such a lowpass filter card with four lowpass filter/splitter circuits thereon, for insertion in a slot of the upper portion 22 of the shelf 10 of Figure 1.

9.

r Figure 7C shows a front view of the card of Figure 7B, as seen from the front of the shelf of Figure 1.

15 Figure 7D shows an optional separate splitter shelf, according to the present invention.

Figure 8 shows a separate splitter shelf, such as that of Figure 7D, used to add XDSL service to an existing DLC, according to the present invention.

.9 o.

Figure 8A shows an ADS remote cabinet, such as shown in Figure 8 in more detail, wherein the configuration shows supports up to 96 lines in a type 3002 cabinet.

20 Figure 9 shows a compact XDSL shelf, in this case, an ADS RAM (remote access mux) shelf, according to the present invention.

Figure 10 shows a functional block diagram of an LT card, according to the present invention.

Figure 10A shows a front view of an LT card.

Figure 10B shows a side view of an LT card.

Figure 11 shows a simplified block diagram illustration of a channel of an LT card in a shelf connected to a subscriber ADS modem via a twisted pair, according to the present invention.

Figure 12 shows an example of frequency allocation of the telephony and the QAMmodulated subchannels (tones) individually optimised as a function of line impairments, according to the present invention.

Figure 13A shows a simplified block diagram of an ADSL modem for use in a subscriber's premises, according to the present invention.

004061512v7.doc 6 Figure 13B shows the exterior of a physical embodiment of an ADSL modem such as shown in Figure 13A.

Figure 13C shows an LED layout for the modem of Figure 13B.

Figure 13D is a table showing the meanings of the various LED indicators of Figure 13C.

Figure 13E shows a more detailed functional block diagram of an ADSL modem for use in a subscriber's premises, according to the present invention.

Figure 14A is a simplified block diagram illustration of an NT card, according to the present invention.

Figure 14B is a table illustrating some of the downstream and upstream functions of the 10 NT card of Figure 14A.

Figure 14C shows a front view of an NT card, according to the present invention.

Figure 14D shows a side view of an NT card, according to the present invention.

e e..

Figure 14E shows a more detailed block diagram of an NT card, according to the present invention.

15 Figure 14F shows a cell header structure for an ATM cell which is the main entity which *eee is conveyed through an ATM network.

Figure 14G is a table showing the routing of received ATM cells depending upon certain bits in the cell header, combinations of which can be checked according to the modes shown in the table.

20 Figure 14H shows an IQ bus cell layout, according to the present invention.

Figure 15A is a block diagram of an ADS Alarm Control Unit (ACU).

Figure 15B lists the functions of the signals of the ACU of Figure Figure 16 shows an actual physical embodiment of an ACU card for insertion in the rightmost slot of the shelf of Figure 1.

Figure 17 is a side view of the ACU card of Figure 16.

Detailed description of preferred embodiments Figure 1 shows a new shelf arrangement 10 for use in a subscriber access multiplexer system according to the invention. The embodiment shown is for use in an ATM subscriber access multiplexer (ASAM) system, but it should be understood that the invention is not limited to ATM embodiments. The shelf 10 is populated by at least one or a redundant pair of network termination (NT) cards 12a, 12b, up to twelve XDSL, in this case ADSL (Asynchronous Digital Subscriber Line), line termination (LT) cards 14, an equal number of Low Pass Filter (LPF) cards 004061512v7.doc 7 24, an optional Network Element Processor (NEP) 16a (or an optional redundant pair 16a, 16b), and an Alarm Collection Unit (ACU) 18. An LT card is described in more detail below in connection with Figure 10, while a network termination card is described in more detail below in connection with Figure 14A-14E. A lowpass filter card is disclosed in more detail below in connection with Figs. 7A, 7B and 7C. An alarm collection unit (ACU) 18 is shown in block diagram form in Figure 15, and a physical embodiment is shown in Figure 16.

These cards can be mounted as shown in Figure 1 in a bottom section 20 of the shelf and can be, eg., six rack spaces in height where one rack space equals 1.75 inches (4.45 cm). An upper portion 22 of the shelf can be, eg., three rack spaces in height for containing up to, eg., 10 twelve lowpass filter (LPF) cards 24, with each LPF card dedicated to an associated ADSL-LT directly below it. Also in the upper portion 22 of the shelf 10 may be located connections 26 for POTS (plain old telephone service) interfaces and connections 28 for drop tip/ring leads, connections 30 for power, and a small board 32 for DS-3-NT equipment protection as explained below. The POTS can, but need not, be in analog baseband form. It could take other forms, such :15 as ISDN. Note that the lowpass filters 24 are grouped in the centre of the upper portion 22 of the shelf, with the connections 26 for POTS and connections 28 for drop tip/ring leads for location at ends 33 of the upper portion 22 of the shelf. Since the lowpass filters plug into the backplane .o *o upon insertion in slots of the shelf and do not connect to cables, they are positioned in the centre oO• of the upper portion 22. The connections 26, 28, 30 and 32, on the other hand, require cabling 20 access and are positioned, according to the present invention, at the ends 33 to facilitate such connections near the periphery of the shelf 19, rather than requiring cables passing over central portions of the shelf. Similarly, the LT cards 14 are positioned in the centre of the lower section of the shelf 10, since they do not require cabling and are connected to other modules by the backplane, to which they are connected via a connector upon insertion. Thus, the NTs 12A, 12B, the NEPs 16A, 16B and the ACU 18 are positioned at ends 35 of the lower section 20 to provide easy cable access. It is also noted that the shelf is designed entirely for front access. The shelf can be dimensioned to fit both U.S. and European equipment racks, eg., being 498 mm wide and 285 mm deep.

The ADS-LTs and the LPFs are dimensioned as four lines per card. As such, a basic shelf supports forty-eight ADS lines in a physical configuration shown in Figure 1.

Figure 1A shows a front view of an actual shelf with redundant NT cards, 12 LT cards, 12 corresponding LPF cards, and an ACU card all inserted therein. Figure 1B shows a plurality 004061512v7.doc 8 of shelves mounted in a central office rack, such as shown in Figure 1E, in a standard configuration for serving 192 ADS lines. Up to four adjacent racks can share the same feeder by using extension units installed in place of NTs, as explained below in connection with Figure 6.

In that case, a single, optionally-protected NT card can support up to 576 ADS lines. Figure 1C shows the shelf of Figure 1A without any cards installed and shows the connectors installed in the backplane, into which mating connectors on the cards are insertable by sliding the cards into the slots shown. In this way, front-access-only is achieved. A side view of the shelf is shown in Figure 1D.

It should be realised that without modification the LTs could be located in the upper 10 portion and the LPFs in the lower portion. Similarly, the various power and connection sections can be located other than as shown exactly in Figure 1. Thus, the ATM subscriber access S multiplexer (ASAM) shelf described above, although unique, can have additional as well as other physical and packaging arrangements to fit particular applications. In addition to the abovedescribed front-access-only shelf compatible with both U.S. and international racks, the above- :15 described shelf facilitates high density, ie., small volume per line design. Also included is a S practical high-speed (155-622 Mb/s) backplane data bus. It contains a simple, flexible shelf ID (identification) mechanism. connectorization and wiring is designed for future BITS capability.

SIt satisfies both U.S. and European electromagnetic compatibility (EMC) requirements. It includes card arrangement for NT and LT cabling for TWP, coaxial, or fibre.

20 As suggested above, it can be utilised as a full sized LT shelf for maximum density and minimum cost, as shown in Figure 1B for a CO, or as described more fully below in connection with Figure 9 as a mini-sized shelf for small remote sites.

The POTS lowpass filters (LPF) 24 of Figure 1 can be passive filters that are contained as shown in separate units for ensuring POTS immunity to XDSL failures, maintenance and "churn" as well as for lower digital/analog crosstalk. In other words, an LT card or any other aspect of the ADS channel can be maintained without disturbing the POTS. Consequently, overall performance is increased.

A functional block diagram of an LT/LPF pair from the group 14, 24 of Figure 1 is shown serving a single copper pair 36 in Figure 2. Although only a single twisted copper pair 36 is shown, it should be realised that the preferred embodiment includes four twisted copper pairs per LT/LPF card pair. In other words, the LT/LPF blocks shown within the ADS shelf section 34 will be replicated four times for each such LTJLPF pair shown in Figure 1 (See the LT card of Figure 004061512v7.doc 9 As seen in Figure 2, an ADS data stream formatted as ATM cells are transported over the copper pair 36 formerly used for telephony only (POTS service) in an overlay fashion, through the use ofhighpass filters 38, 39 and lowpass filters 40, 42 at both the ADS shelf to the left of a dash line 44 and at the subscriber premises on the right side of the line 44. The line 44 signifies the place where copper distribution to the subscriber begins. Normally, the ADS shelf section 34 will be part of a shelf 10 such as shown in Figure 1A within a rack in a central office, as shown in Figure 1B, within which office also resides a CO switch 46 and a broadband switch such as a packet switch, eg., an ATM switch 48. The broadband switch could be located elsewhere, such 10 as further upstream. The CO switch 46 is for connection to a switched telephone network, such as the public switched telephone network (PSTN) for providing POTS service on a line 50 to the twisted copper pair 36 and into customer premises via copper wires 52 at the customer end, as shown in Figure 2 on the right-hand side of a dashed line 54, signifying a customer premises boundary, for connection to a telephone 56 for normal voice communication. However, the ADS 15 shelf 34 could just as easily be located in a remote cabinet in association with a DLC (Digital *o Loop Carrier) shelf, as described further below, with both ATM traffic and POTS being carried to it, eg., by a SONET (Synchronous Optical NETwork) transport product.

*.oee The ATM switch 48 is for connection to an ATM network which provides connection to various services, including Intemrnet Service Providers (ISPS) and other high bandwidth service 20 providers. The ATM switch 48 provides ATM formatted data on a line 58 to a network termination (NT) card 60 which is, in turn, connected to a plurality of ADS line termination (LT) cards such as the card 62 which includes the highpass filter 38 for providing the ADS signal on a line 64 to a junction node 66 for combination with the normal telephony signals provided by the lowpass filter 40. The node 66 thus forms a means for frequency division multiplexing, ie., joining the POTS service on the line 50 at a low frequency with the high bandwidth services provided on the line 58 and converted to ADS by the LT 62 at a higher frequency for passing through the filter 38 and on to the line 64 for combination with the telephony service at the node 66 of the twisted copper pair 36. Figure 12 (not to scale) shows an example of bandwidth allocation for POTS service at baseband, eg., 0-4 kHz, with DMT technology used for the ADS signal between 40 kHz and 1.1 MHz. In this case, the spectrum allocated for use downstream is much larger than that allocated for upstream, and hence the designation as "asymmetrical" digital subscriber line (ADS).

004061512v7.doc Referring back to Figure 2, at the customer end 54, a node 68 allows the signal on the line 36 to be split off on a line 70 before passing a telephony signal through a lowpass filter 42 in a Network Interface Device (NID) (not shown). The ND can be an enclosure (box) for mounting on the wall of a house, and both the node 68 and LPF 42 can be inside the NID. The line 70 is connected to an ADS modem 72 which highpass filters the signal on the line 70 and demodulates and decodes the ADS signal for providing a high bandwidth signal on a line 74 to customer premises equipment such as, but not limited to, a personal computer (PC) 76. The NID enclosure can be, for example, as shown in copending and co-owned patent application filed on even date herewith entitled 11 Apparatus for Mounting a Low Pass Filter in a Telephone Network Interface 10 Box" having U.S. Serial No. (Atty. Docket No. 907-158).

It should be mentioned that the POTS signals in the baseband part of the signal spectrum of the signal on the line 36 of Figure 2 can include conventional analog modem and even Smechanised loop testing (MLT) signals, neither of which will be degraded by or affect the ADS service.

:15 The functional block diagram shown in Figure 2 illustrates both the data and telephony paths to the customer. The shelf (basic shelf) architecture is further illustrated in Figure 3. The basic shelf 10 includes an "IQ bus" including control leads 78, which is more fully described in copending U.S. provisional patent application Serial No. (Atty. Docket No. 902-583) entitled i: "Method for Prioritized Data Transmission and Data Transmission Arrangement", filed on even 20 date herewith and which is hereby incorporated by reference. As was known in the prior art, whenever a number of any kind of terminal units need to access a common medium or bus, some access grant criterion is needed, eg., upon a grant signal, each terminal unit enters an arbitration phase based on the respective priority values assigned to the terminal unit. The problem with this is a problem of fairness, in that the terminal having a low priority might never get access. In brief, and as illustrated in Figure 3A, the IQ bus invention makes the priority adaptable after each grant cycle, so that if a unit does not get access, its priority can be increased. In addition, the priority value can be linked to an access mode requested by the terminal unit, eg., a Guaranteed Cell Rate GCR (CBR, VBR, ABR in case of an ATM-based bus), Non-Guaranteed Cell Rate NGCR (VBR, ABR, EBR in case of an ATM-based bus) by allocating value ranges to each access mode, increase of the priority then being limited by the boundaries of the respective ranges. For instance, five different levels of QoS classes are shown at the left-hand side of Figure 3A, with the lower three classes having both guaranteed cell rate and nonguaranteed cell rate subclasses indicated.

004061512v7.doc 11 Naturally, the constant bit rate (CBR) and variable bit rate-real time (VBRrt) classes do not have non-guaranteed cell rate (NGCR), since they must be guaranteed. The nonguaranteed cell rates are shown grouped at the bottom of the priority mapping to the right, which shows QoS subclasses with guaranteed subclasses at the top (shaded). Nevertheless, according to the present invention, overbooking of non-guaranteed bandwidth is allowed by providing not only prioritization, as shown, but also an aging mechanism, as shown on the far right of Figure 3A.

When a terminal subscribing to a non-guaranteed class of service does not get access within a predetermined period, its priority is increased according to a selected algorithm to a value within a range corresponding to an access mode having a higher access probability. One particular and 10 non-limiting way of defining priority values is suggested in Figure 3A, with 2"-1 priority values defined and evenly allocated (for instance) among the QoS subclasses. As an example, for a hardened-UBR QoS class, the guaranteed cell rate (GCR) is normally defined as a number of cells per second. A period having a time defined by the inverse thereof can thus be defined as shown in Figure 3A, indicating how the priority of the cell from the lowest subclass (NonGuaranteed :15 Hardened UBR) can be increased after it is not granted access to the bus after a waiting time T IGCR seconds. In the example shown, the priority is increased in a single step to that of the Guaranteed Hardened UBR subclass, thus statistically implementing a minimum cell rate for the Slowest subclass. These teachings advantageously provide a flexible method allowing access based on a type of access mode and on agreed access parameters. The IQ bus is thus distinguished by S. 20 a unique grant mechanism and fairness algorithm. It provides multiple QoS classes with multiple cell priorities per class. It features a cell aging priority mechanism, as well as a QoS priority mechanism to ensure cells comply with the class of service parameters defined in Bellcore Specification GR-1110. It is provided with fault tolerance and recovery mechanisms, allowing any fault on the multiplex bus to be quickly identified and isolated. It has a redundant extension capability as well, as described below in connection with Figure 6. The IQ bus builds upon an earlier bus" (without QoS) described in copending U.S. provisional patent application Serial No. (Atty. Docket No. 902-581) entitled "Priority-Based Access Control Method and Arrangement", filed on even date herewith, and which is also hereby incorporated by reference.

As shown in both Figs. 1 and 3, the NTs 12a, 12b can be provided in either a redundant or non-redundant configuration. In this architecture, the normal NE processing is performed by the NT, and the NT can be provided as either a SONET User Network Interface (UNI) interface, a DS-3 UNI interface or later, a DS1 inverse multiplex UNI interface. If SONET NTs are 004061512v7.doc 12 provided as redundant pairs, Automatic Protection Switching (APS) is provided using the normal 1+1 switchover mechanism detailed in Bellcore document GR-253. On SONET NTs, the physical interface (fibre) is located on the faceplate of the NT itself(see Figs 14C and 14D), with no need of additional interface circuitry. If, however, NTs are provided as DS-3 ports, equipment protection (without cable protection) is provided using the DS-3 I/0 board 32 shown in Figure 1 installed above the NTs in the shelf, allowing the single DS-3 facility (coax cable Tx/Rx pair) to be split and accessed by either NT (inter-NT communication arbitrates which one is active).

From the foregoing it will be appreciated that the heart of the ADS shelf architecture is the abovementioned IQ bus and control leads 78. The IQ bus effectively acts as a multiplexer at *10 the same effective speed as the NT physical interface. Since ADS-LTs provide several classes of service (as defined in Bellcore document GR-1110 and the ATM Forum Standards), a grant mechanism allows higher priority upstream cells greater access to this ATM MUX bus, in order .999 to meet the QoS parameters required of the respective services provided. As mentioned, two methods of cell priority can be chosen to guarantee QoS requirements and relative fairness--a 15 weighting priority mechanism (based on service guarantees) and an aging mechanism (based on time a cell has been waiting for a grant). This mechanism is unique and the subject of the abovementioned provisional application Serial No. (Atty Docket 902-583), which has been incorporated 9.

by reference.

•The ACU 18 in Figure 3 is shown in block diagram form in Figure 15, and it performs the i 20 following functions: collects external customer designated alarm contacts on lines 80 and forwards these events to the NT 12a via lines 78; collects failure indications in the rack and forwards this information to the NT 12a; receives processed alarm data from the NT and displays the alarm condition (critical, major, minor) on the ACU's faceplate as well as providing contact closures for visual and audible (and telemetry alarms) to a rack fuse panel and to a CO alarm interface via a line 82. The ACU also contains: an alarm cutoff (ACO) function to silence audible indications until a new alarm is detected (as well as a remote ACO function via line 82); a craft interface port 84 for controlling OAM and P functions of the ADS NE (using a link to the processor in the NT); an ethernet port for OS connection via the NEP; and (7) a lamp test function. One ACU card is provided per rack when a system spans multiple racks. An ACU is provided per NT (or redundant NT pair) when multiple systems reside in a given rack. Multiple systems reside in a given rack when a very wide bandwidth is to be served by, eg., a single shelf. In such a case, a single shelf may use up the entire bandwidth of an OC-3 004061512v7.doc 13 or DS-3 cable.

As shown in Figs. 3 and 10, each ADS LT 14a, 14b, 141 communicates with up to four remote modems (ADS NT or ANT) at corresponding customer premises via DMT (Discrete Multi-Tone) per T1.413 (see Figure 12), using ATM cells as the data transport format, according to the present invention. The subscriber can have a lowpass filter (LPF) 42 mounted, for example, on the outside wall of his home in an NID (Network Interface Device) box to separate the low frequency service (telephony) from the higher frequency services (ADS). As mentioned, a way to mount such an LPF within an existing design NID is shown in copending application U.S.

Serial No. (Atty. Docket 907-158) filed on even date herewith and which is hereby incorporated 10 by reference. The two services, once split, use different twisted pairs in the house wiring, with the ADS pair terminating in either an ANT or directly in a PC via an NIC (Network Interface Card). ANTS, for example, can come in two types: one with an ATMF 25.6 Mb/s interface, the other with an ethernet interface (in this case the ANT packages the ethernet data as ATM cells using AAL5 (ATM Adaptation Layer 5) protocol). Both options can be provided on the same 15 ANT, as shown in Figure 13B.

The basic shelf 10 also contains, as shown in Figs. 1 and 3,1 an optional network element processor (NEP) redundant pair 16a, 16b, which communicates over the IQ bus 78 mechanism S e and communicates with its redundant partner over separate leads 86 to determine which one is active. The NEP can terminate signalling channels for SVC (switched virtual connection) services S: 20 or PVC (permanent virtual connection) services and can terminate the ACU ethernet port.

Presently, the two NEP cards 16a, 16b of Figs. 1 and 3 are not being implemented, although there are two slots reserved for it. It is planned to be available later for terminating and processing SVC (Switched Virtual Circuit) signalling channels, and for providing an ethernet termination for the ACU ethernet port. There are no other functions presently planned for the NEP cards.

As shown in Figure 4, the basic shelf 10 may also be used as a "hub" shelf 90, with one or more ADS-LT slots populated by DS-3-LTs or other cards such as OC-3, DS-1 inverse mux LTs, etc. Each DS-3-LT connects the hub to a concatenated "remote" ADS shelf 96, 98, as shown in Figure 4. In such cases, for the hub, the IILPFII modules above the DS-3-LTs are replaced with DS-3-LT interface modules (one type for nonredundant operation and another type for redundant DS-3 "equipment protection" operation).

A third type ofDS-3 LT interface module can be provided for redundant IQ bus operation, with 004061512v7.doc 14 the DS-3-LTs being on separate shelves for reliability purposes (due to there being only one IQ bus per shelf). The present architecture uniquely provides for each of these redundancy options.

As shown in Figure 4A, the LT-LPF backplane wiring is shown with LT transceivers. In this case, the LPF and LT cards can be configured for redundancy of the LT cards to be inserted in the LT slots in either a same shelf or in separate shelves. For example, in Figure 4B, a nonredundant option LT is shown with a DS-3 interface inserted in LPF slot 1, wherein input and output DS-3 coax cables from a CO switch are connected to a DS-3 interface card for insertion in LPF slot 1, which is connected through the backplane to a DS-3-LT card for insertion in LT slot 1, such as the DS-3-LT card 92 of Figure 4. The lowpass filter function is carried out at the 10 remote shelf 96 of Figure 4 where a DLC is available. The configuration shown in Figure 4B for LT slot 1 and LPF slot 1 could also be used in connection with Figure 4E, as explained below.

Figure 4C shows an application with redundant DS-3-LT cards for insertion, eg., in LT slot 1 and LT slot 2 of a given shelf. In that case, a different kind of DS-3 I/0 card is used, double wide as shown, with a centre tapped transformer on the card which is connected both to the 15 transmit (TXA/TXB) and to the receive (RXA/RXB) backplane wiring associated with both LPF slot 1 and LPF slot 2. The NT controls which LT slot is to be active.

Figure 4D is similar to Figure 4A but additionally shows arbitration interfaces between Sredundant DS-3-LTs.

As suggested above, since there is only one nonredundant IQ bus per shelf, the equipment 20 protection implied by Figure 4C with A and B redundant DS-3-LT cards in slots 1 and 2 will be ineffective if the IQ bus itself has a failure. If it is desired to avoid this sort of failure, a different kind of redundancy in the DS-3 cards can be provided, as shown in Figure 4E. In that case, half of the transmit and receive signals are used in the shelf, and the other half can be routed to a different shelf, instead of slot 2 in the same shelf. The top two cables shown in Figure 4E would thus be routed to another shelf and be connected into, eg., the DS-3 out and DS-3 in transformers shown in Figure 4B in another shelf. The DS-3 out and DS-3 in cables of Figure 4E would go to the CO switch or other network element.

As will be observed in Figure 4, an ADS shelf 90 may have both ADS-LTs 14a and aggregate type LTs such as the DS-3-LTs 92, 94 shown. Service classes in both cases are provided for subscribers by separate buffers per service class (CBR, VBR, UBR, etc.), each contending for upstream access to the IQ bus via the control leads and the grant mechanism based in part on the priority assigned to each upstream cell. In the case of aggregate LTs, such as shown 004061512v7.doc in the hub 90 of Figure 4, the service class buffers have a cell priority equal to the sum of the aggregate cell priorities in each buffer (or even some percentage), in order that the remote subscribers are assigned a fair share of the hub's operating bandwidth. In times of bursty upstream traffic, congestion and DS-3-LT buffer overflow is managed by limiting the DS-3 link bandwidth and allowing temporary buffer fill in the remote ADS-LTs (until such time that the traffic peak subsides). It is noted that POTS interfaces are not shown in Figure 4 but would normally be provided, eg., by DLCs adjacent or incorporated in the Remotes 96, 98.

Figure 5 shows the hub 90 of Figure 4 located in a central office 100 which may also include a CO switch 102 and an ATM switch 104. The CO switch is connected to a public switched telephone network (PSTN) 106 and the ATM switch to an ATM network 108 which is, in turn, connected to other services 110 which may include various Internet service providers 112, 114. As illustrated in Figure 4, the hub shelf 90 may be populated by both ADS LT cards such .eo Sas the card 14a and various other cards including DS-3 LT cards 92, 94. Four copper pairs emerging from the ADS LT card 14a of Figure 4 are illustrated as a plurality of copper pairs 116 15 in both Figs. 4 and 5. These leads provide an ADS link directly between the hub and the various customer premises illustrated, including a customer premises 118 shown in detail. If the shelf were used exclusively with ADS LTs 14, such as shown in Figure 1, all of the subscriber lines Swould be like the lines 116 without using the shelf 90 as a hub and without the remotes of Figure i. 5. In other words, there would be twelve groups of 4 POTS plus ADS lines 116 serving 48 20 different customer premises. The implementation of Figure 5 provides for many more customer premises served by a single shelf, but with the accompanying increased competition for upstream bandwidth. This can be tolerated in cases where the majority of subscribers are using lower quality of service.

A lowpass filter 120 is mounted in a network interface device arrangement (not shown) for terminating the subscriber line at the customers premises. It filters out all but the low frequency telephony signal from the copper pair and provides it on a line 122 to a traditional telephone 124 for voice communications. It also filters high frequency dial pulse or ring trip transients so that they do not interfere in the upstream direction with the high-speed data traffic.

A second copper pair connected before the lowpass filter, as shown, is provided to an ADS modem 126 which, after highpass filtering, demodulates and decodes the ADS signal and provides output bits on a line 128 to a user terminal 130 such as a personal computer, Internet computer, etc., eg., for Internet access or for access to other high bandwidth services 110. It 004061512v7.doc 16 should be realised that the ADS modem also operates in the reverse (upstream) direction, albeit in a much narrower bandwidth, to encode and modulate bits onto the ADS line from the subscriber to the ATM network as per ANSI T1.413 (see Figure 12).

The remote shelves 96, 98 of Figure 4 are also shown in Figure 5 connected to various customer premises, which are similar to premises 118.

Figure 6 shows in detail the above-mentioned feature of the present architecture whereby a plurality of ADS shelves 10a, 10b, 10Oc, 10Od such as shown in Figure 1 can be daisy-chained together in a rack by means of an extender card (EXT) in each subsequent shelf. The extender card function is to effectively extend the IQ bus from shelf to shelf (daisy-chained, eg., to a 10 maximum of twelve shelves altogether), allowing up to, eg., 576 ADS subscribers accessed to the system. In other words, the extender card allows an NT card in a first shelf to act as an NT card •for another shelf or a plurality of other shelves. in this case, three racks with altogether twelve Sdaisy-chained shelves. The extender cards can be mounted as shown in Figure 6 in the NT slots of subsequent shelves and may be redundant. In that case, any failure of an NT or extender card 15 bank switches all LTs from the "All NT/extender string to the string. The active string then assumes control of each shelfs IQ bus. The IQ bus itself(within each shelf) is not redundant, but meets reliability requirements, as the NT has the ability to remove each LT from the IQ bus 0 (disable) to isolate a fault and remove it from service.

As suggested above, the POTS lowpass filters can be provided for different options 20 including "integrated" in a CO shelf for maximum packaging density, minimum cabling and installation complexity and minimum cost as described above or "separate" (remote, nonintegrated) for regulatory flexibility and access to existing (crowded) DLC cabinets.

Figure 7A shows a lowpass filter card, such as one of the LPF cards 24 shown in Figure 1 in schematic block diagram form. Four different lowpass filters/splitters are shown on the card.

To the left of each card is a voice port for connection to the narrowband (NB) network via the CO switch 46 via the line 50. on the right-hand side of each lowpass filter/splitter is a port which is connected both to the twisted copper pair 36 to the subscriber and to the highpass filter 38 of the LT 62 (see Figure A side view of the physical dimensions of such a four-channel LPF card is shown in Figure 7B, while a front view is shown in Figure 7C.

Figure 7D shows a splitter shelf for use in applications where the lowpass filters need to be remote from the ADS shelf. Such a shelf can be used, for example, when separate service providers are responsible for the telephony and ADS services, or in DLC (digital loop carrier) 004061512v7.doc 17 configurations where remote cabinets of DLC equipment cannot accommodate ADS equipment (due to lack of physical space), but since the subscriber transmission pairs terminate in the DLC cabinet (and enough room is available for a small lowpass filter "splitter"), this shelf only is installed in the DLC cabinet.

In this case, the basic XDSL shelf is used, as previously shown, but with the LPF boards not populated. A separate "splitter" shelf, as shown in Figure 7, is then provided and has a configuration the same as, or very much like, the top portion of the basic XDSL shelf 10 of Figure 1. The main difference in remote splitter configurations is the cabling and the use of"stackable" connectors. The splitter shelf is shown in Figure 7, and a typical configuration using splitter 10 shelves is shown in Figure 8. In an initial implementation, LPFs (and the splitter shelf) need no power, as all circuitry is passive.

•Figure 8A shows a remote cabinet that can be used when adding ADS service to existing Smetallic-fed DLCS. This configuration supports up to 96 lines in a type 3002 cabinet.

It should be noted that the "separateness" of the lowpass filters 24 as shown in Figure 1 :15 from the LTs, as well as the separateness of the LPFs of Figs. 7, 8 and 8A is not only advantageous for the reason mentioned above, ie., for facilitating separate service providers for telephony and ADS services, but also for the very important reason, according to the present o invention, for physically separating the lifeline telephony service from the ADS service. Such separateness provides an increased level of integrity for the lifeline POTS service, since such S: 20 physical separateness itself ensures that any maintenance actions which may need to be performed on the ADS part of the system can be done in a physically separate manner, and therefore in such a way as to not affect the POTS service (and vice versa).

Another equipment shelf is the RAM (Remote ADS Mux) shelf as shown in Figure 9.

This shelf is deployed very much like the remote ADS shelves 96, 98 shown in Figure 4, and in fact may have the same shelf architecture as that shown in Figure 3. The difference is that the RAM shelf is more suited for CPE or DLC applications where, eg., no more than twenty-four lines are required, and a smaller shelf (6RS versus 9RS) is desired. As such, a RAM shelf may be designed and physically configured, for example, as shown in Figure 9. This shows the flexibility of the XDSL shelf of the present architecture.

Figure 10 shows a functional block diagram of one of the ADS LT cards 14a of Figs. 1, 3 and 4. The implementation of the various functional blocks is realised in this implementation by the application of an ADS chip set of assignee for DMT technology. This chip set consists of 004061512v7.doc 18 three chips (integrated circuits) identified as RCHAP for ATM functions, a DACHA/SACHA chip for Reed Solomon coding and decoding, and a front-end DSP chip called ADSLB. The remaining blocks are preferably carried out by other means outside the chip set. The three chip set RCHAP, SACHA and ADSLB are also shown in Figure 11 in a simplified block diagram that shows the chip set in both an LT 14a in an ADS shelf 34 and in an ADS modem 72 at a customer's premises in reverse ordering of chips.

In regard to the ATM functions carried out by the RCHAPB chip, such takes care of the encapsulation of ATM cells in 54-byte slots and the access to two separate IQ buses, ie., upstream and downstream. There is also a dummy cell added to the 53 standard ATM cells in order to allow 10 a change-over from one LT to another on the upstream IQ interface (between cells). On the downstream IQ interface, this byte is not filled in, and on the upstream IQ interface, the bus is in high impedance state during this byte.

*oo•* i n The main entity which is conveyed through an ATM network is a cell which is divided into two parts, each with a fixed size: the header (5 bytes), and the information field (48 bytes).

S: 15 Depending on the value of the header of the ATM cell, a number of ATM-related functions may be performed, such as insertion and extraction of maintenance cells, cell rate decoupling, Header Error Control (HEC) generation/check, payload scrambling, cell loopback, etc.

S °The data that are sent on the ADS line are forward error- corrected (FEC) by Reed Solomon (RS) coding to improve the bit error rate. To allow for an even better protection against S 20 burst errors an interleaving possibility is incorporated, with the disadvantage of an increased transfer delay for interleaved data. Also, a scrambler is included to randomise the data before the RS encoder. After the RS decoder, the data is then descrambled.

Also carried out by the SACHA chip set, besides Reed Solomon (de)coding is mapping and demapping. In the ADS system, a DMT approach may be followed in which, for example, up to two hundred fifty-six carrier frequencies can be used (see Figure 12). Each of these frequencies will carry a number of bits according to a mapping table. The function of the mapper is to assign the bits to the different frequencies. The mapper can also send some special DMT symbols for link initialisation and maintenance. The demapper will demodulate and monitor the received symbols. After demodulation, it delivers the data to the on-chip RS decoder. Some special functions are included in the demapper for initialisation and maintenance of the ADS link.

An example of an ADS mapper is shown in Figure 1 of copending and co-owned application Serial No. 08/677,468, filed July 10, 1996 and described at page 7, line 5, through page 9, line 004061512v7.doc 19 23.

A similar description is given in copending provisional application Serial No. (Atty.

Docket No. 902-575) filed on even date herewith, entitled "Method and Windowing Unit to Reduce Leakage, Fourier Transformer and DMT Modem Wherein the Unit is Used", at page line 10, through page 7, line 26 thereof.

The output of the mapper is a complex representation of all the carrier frequencies. An Inverse Fast Fourier Transformer is used to transform this representation to a time signal. In cooperation with the IFFT, a carrier selective scaling can be installed. In the upstream direction, an FFT is used to transform the received time signal to a frequency representation.

10 The main function of the front-end digital signal processing is to separate the received signal as much as possible from the transmitted signal, and to correct for the line and analog front-end characteristics.

The ADSLB chip function includes analog-to-digital (AJD) and digital-to-analog (D/A) conversion. The function of the subscriber line analog front end is the termination of the analog :15 line interface and the transformation of the digital data into an analog passband signal that can S be transmitted on a physical subscriber line 36 and vice versa. For the D/A and A/D conversion, a sigma-delta (EA) approach is used.

As shown in Figure 11, the subscriber line analog front-end function includes a line driver used to amplify the ADSLB output to the levels appropriate to be transmitted over the subscriber S 20 line. A hybrid is included as a passive network that performs the termination of the subscriber line with its nominal impedance and handles the conversion between four-wire and two-wire in the LT at the upstream end. It performs the separation in the upstream direction between the upstream and downstream signals, and the combining in the downstream direction. The reverse is performed at the downstream end of the line.

Referring back to Figure 10, it is noted that the LT 14a includes four separate line termination paths for four separate subscribers. Although not shown in Figure 10 or 11, it should be realised that the twisted pair connects not only to the HP-filter and hybrid shown in Figs. and 11, but also to a lowpass filter 40, such as shown in Figure 2. Figure 10A shows a front view of an LT card, while Figure 10B shows a side view.

Since POTS signals and ADS signals are transported frequency-multiplexed on a subscriber line, as shown in Figure 12, a POTS lowpass filter 26 is required, which performs the following functions: combining the POTS and ADS transmit signals toward the subscriber 004061512v7.doc premises; separating the POTS and ADS signals from the subscriber premises; protecting the POTS from audible interference, generated by signals from the ADS modem and the ADS shelf; and protecting the ADS receiver from all POTS-related signals, particularly dial pulses, ringing and ring trip transients.

These functions are performed while meeting all the requirements for POTS performance, such as return loss, insertion loss and group delay, such as those in ANSI Standard T1.413. The combination and separation of POTS and ADS signals is achieved by lowpass and highpass filtering, as shown in Figure 2. Only the highpass filter and the hybrid are part of the LT. As mentioned above, the lowpass part preferably resides on a different printed board assembly (LPF).

10 Also shown in Figure 10 is an on-board controller (OBC), which may be embodied as a microprocessor included to handle a variety of tasks, such as initialisation of ASICS, monitoring and processing of maintenance messages, and detection of a malfunctioning LT. On-board memory may include flash-PROM and DRAM used for executable code and data. Inventory o• information may also be stored on an EEPROM so as to provide the necessary data for an S. 15 adequate identification of a replaceable item. Such may include product identification, manufacturing information and inventory information. Also shown in Figure 10 are power supply functions by way of on-board mounted DC/DC converters. A test access port (not shown) may Salso be provided.

As will be understood by anyone of skill in the art, from American National Standard for 20 Telecommunications "Network and Customer Installation Interfaces--Asymmetric Digital Subscriber Line (ADS) Metallic Interface", ANSI T1.413-1995, the nature of the signal on the twisted pair 36 shown in Figure 11 and in Figure 2 may be a standardised asymmetric digital subscriber line signal that allows the provision of plain old telephone service (POTS) and a variety of digital channels. In the direction from the network to the customer premises, the digital channels may consist of full duplex low-speed channels and simplex high-speed channels; in the upstream direction, only lowspeed channels are provided. The transmission system is designed to operate on two-wire twisted metallic cable pairs with mixed gauges. The standard is based on the use of cables without loading coils, but bridged taps are acceptable, with the exception of unusual situations. As shown in Figure 12, for example, the power spectrum is shown as including a 4 kHz band reserved for POTS service, with the portion of the spectrum between kHz and 1.1 MHz occupied by a large plurality of carriers, with tone spacing of 4.3125 kHz. A small portion of the spectrum is used for upstream data, as shown, with the remainder used for 004061512v7.doc 21 downstream data. Each of the 4 kHz tones is QAM-modulated and individually selected and optimised as a function of individual subscriber line characteristics. Some tones are allocated with a large number of bits, while others a lesser number or none at all, due to line conditions.

As shown in Figure 11, the functions already described in connection with an ADS LT 14a are replicated in the ADS modem 72. In addition, a selected interface to the subscriber PC 76 may include, eg., an ATM-25 and/or Ethernet interface, as shown in Figure 11.

Figure 13A shows a simplified block diagram illustration of an ADS Network Termination (ANT) unit. It includes a modem part which performs the ATU-R transmitter reference model functions, for example, as shown in Section 4.3 of ANSI T1.413-1995. An ATM function is added, according to the present invention, for ATM translation and signal processing.

In the downstream direction, the ANT unit terminates the ADS signal, demodulates, and the interconnect function converts the ATM cells into a digital bitstream to the subscriber's digital terminal equipment (DTE). In the embodiment shown, the interfacing block to the customer equipment includes both ATM and/or ethemet interfaces, as shown. Figure 13B shows an ADS 15 Network Termination Unit with the line, ATM and ethemet connections shown. The line connector is RJ14, while the ATMF-25 and 10BaseT connectors are RJ45. Figure 13C shows five LED indicators that are visible on the top of the box of Figure 13B for giving the indications indicated in the table of Figure 13D.

A more detailed functional block diagram of an ADS modem 72 (such as already shown S. 20 in Figure 11) is shown in Figure 13. The lowpass filter 42 of Figure 2 is shown as part of an external "splitter" in Figure 13, which also includes the node 68 of Figure 2.

An external AC/DC inverter (6V DC/xV AC) and an onboard DC/DC power supply are shown in Figure 13 and are used to feed the power to the board. The external power supply (AC/DC) converts the high voltage from the wall outlet to a voltage that can be handled by the ADS modem 72, such as +6 volts DC. Further conversions are shown from the DC/DC power supply.

An analog front-end may include the highpass filter 39 already shown in Figure 2, as well as a hybrid and line driver such as shown in Figure 11. The hybrid is for 2wire to/from 4-wire conversion.

An ADSLB block is shown for terminating the analog line interface and for transformation of digital data from a DACHA/SACHA block into an analog passband signal that can be transmitted on a physical subscriber line and vice versa. The ADSLB performs analog- 004061512v7.doc 22 to-digital and digital-to-analog conversion.

Again, the SACHA is the DMT signal modulator/demodulator. This software-configured ASIC processes the ATM cells (scrambled) from the RCHAP block and delivers the DMT modulated signal to the ADSLB and vice versa. Note that there is no difference between the DACHA and the SACHA, except a lower cost for the SACHA. A DACHA can be used as well, and is especially necessary to support a standardised 4.3125 kHz tone spacing mode.

The RCHAP provides the interconnection between the SACHA/DACHA and the rest of the system. It contains 16 ATM cell buffers in both upstream and downstream directions, and performs virtual path/virtual channel (VP/VC) translation, extraction and insertion of ATM cells, 10 and handles on-board tasks.

A RAPID block provides interfacing between RCHAP, ATM-izer and IDT-PHY blocks.

It also contains DMA controller and logic for ethernet functions.

The IDT-PHY block translates ATM cells between the on-board parallel data bus (with standard byte-wide cells) and the serial data over the ATM Forum physical connector (with scrambled 15 4B5B coded data).

The ATM-izer is the upstream controller, responsible for upstream quality of service, cell shaping and policing. It is responsible for translating downstream AAL5 packets into ethernet- Sframes and vice versa. Handling upstream ATM Forum data is also performed by the ATM-izer.

An 182596 controller performs CSMA/CD medium-access control, moves ethemet frames 20 between SRAM packet memory and a serial ethemet transceiver. It is monitored by the OBC. An 182503 performs a serial transceiver function to 802.3 10Base-T, direct interface to 182596.

For code processing, an 1960 microprocessor is included to handle a variety of tasks, such as initialisation of ASICS, memories, etc., monitoring and processing of the maintenance messages, on-line/off-line test support. Memory is included in the OBC as well, such as 2 Mb DRAM for program executables and a 1.5 Mb FPROM for boot code, power-on test, a 512 Kb for ethernet packet memory, etc. A small EEPROM (4 kbit) is used for a remote inventor circuit.

Figure 14A shows a simplified block diagram of an embodiment of an NT card, according to the present invention. It provides a high-speed optical or electrical access to a Synchronous Optical Network (SONET) transport system. It converts Asynchronous Transfer Mode (ATM) cells to SONET packets frames) and vice versa. Thus, the NT card adapts ATM cells carried on the IQ bus to the SONET transmission system and vice versa. It also includes necessary functions as listed in the table of Figure 14B for operating and maintaining the ATM subscriber 004061512v7.doc 23 access multiplexer of the present invention.

It is noted that the table of Figure 14B is split into two columns representing downstream functions and upstream functions. The downstream functions, for example, have been grouped and numbered 1-4, and similarly labelled in Figure 14A in the top section of the respective four blocks. Similarly, for the upstream functions, these have been grouped in the right-hand side of the table and have been numbered 5-8, with the same numbers shown in the lower half of the blocks of Figure 14A. It should be realised that these functions can be moved between blocks, and this is just an example.

In regard to the physical medium block, this can be an optical interface for interfacing an S: 10 optical transport system with a receive and transmit optical fibre carrying signals, eg., with a nominal bit rate of 155.52 Mbps. The interface is symmetric, ie., it has the same bit rate in both directions and could operate, eg., at a wavelength of 1.3 gin. This signal can be a SONET (Synchronous Optical Network) signal at the OC-3 level for conversion to STM-1/STS-3c in the electrical domain. This is a serial signal which the physical medium interface block converts to :15 parallel form at a slower rate for processing on the NT card, with the parallel downstream output locked on to the received clock.

The transmission convergence sublayer processing is done in the second block, wherein 5* e the ATM cells are delineated within a hierarchical transmission frame structure used to transport o the ATM cells. These cells are divided into two parts, each with a fixed size, the head with five 20 octets, as shown in Figure 14F, and the payload with 48 octets, as shown in Figure 14H. In the ATM block of Figure 14A, ATM layer processing is carried out. In the upstream direction, all fields in the ATM cells received on the IQup interface are transported transparently, except for the Header Error Control (HEC) field (see ITU-T Recommendation 1.361, "B-ISDN ATM Layer Specification"). The HEC may be checked or not, as an option. The routing of received ATM cells depends upon the VPI (Virtual Path Identifier) and VCI (Virtual Channel Identifier) bits in the cell header. The full VPI octet and the eight least significant bits of the VCI can be checked for VPIiVCI combinations corresponding with a data channel to be extracted. This method provides for a maximum of 2 16 channels which can be marked for extraction. All valid cells received from the IQ interface are transmitted either upstream in a virtual container or synchronous payload envelope (VC-4/SPE, or to an on-board controller.

For downstream ATM layer processing in the ATM block of Figure 14A, each VC-4/SPE carries the equivalent of 44.151 cells (53 octets) which are octet-aligned and floating within the 004061512v7.doc 24 VC-4/SPE. The ATM cell delineation uses the correlation between the Header Error Control (HEC) in the cell header and the cell header itself. The cell delineation mechanism, as recommended by ITU-T Recommendation 1.432, "B-ISDN User-Network Interface Physical Layer Specification", is used. When the ATM cell boundary identification in octet H4 is used, the cell delineation will start searching at the octet indicated by H4. If not, the search will start at the first octet of the payload period. The ATM cell information fields are descrambled according to the selfsynchronizing scrambling/descrambling scheme recommended by ITU-T.

Valid non-idle cells, each with its confirmed HEC octet and descrambled information field, are sent to the IQ down interface, which is the last block shown in Figure 14A. In that 10 block, idle cell periods are added to adapt a received bit rate of up to 149.76 Mbit/s to 152.64 Mbit/s.

The routing of received ATM cells depends upon the VPI, VCI and PTI (payload type *99* identifier) bits in the cell header. In total, 16 bits or four nibbles ofVPI/VCI combinations can be checked, according to the modes shown in Figure 14G. In each mentioned mode, different 15 nibbles of VPI/VCI are selected. The selected VPI/VCI nibble combination corresponds with a specific data channel to be extracted. Cells can be extracted by looking only at the VPI/VCI combination or by looking at the VPI/VCI combination and at the PTI bits. In the second case, each PTI (2 3 in total) can be marked for extraction. This marking will then be used for all VPI/VCI combinations for which extraction is indicated, with the inclusion of the PTI check. All 20 valid cells received in the virtual container or synchronous payload envelope, independent of their VPIJVCI combination, are transmitted downstream on the IQ down interface (cells marked for extraction are also sent to the ATM interface bus).

ATM cell insertion and extraction is provided at the NT both in the direction of the network and in the direction of the IQ bus, in order to provide for the transmission and reception of Operation And Maintenance and signalling cells. Cell insertion and extraction is under control of an On-Board Controller (OBC).

In the upstream direction, the OBC has the possibility of inserting ATM cells in the outgoing VC4/SPE. The OBC has to provide a valid cell header without HEC, followed by a least six bytes and, at most, the complete cell payload (a total of 52 octets). The HEC is calculated before the cell is put into the VC4/SPE. Interfacing between the OBC and upstream cell stream is performed by using a FIFO buffer on which a back pressure signal indicates if the OBC is allowed to insert a cell or has to wait until the previously inserted cell is transmitted. Cells 004061512v7.doc received on the IQ up interface have a higher priority than cells coming from the OBC.

Synchronisation is performed by a synchronisation signal which indicates to the cell insertion device where the boundary between two inserted cells in the FIFO buffer is. Downstream, the OBC has the possibility of inserting ATM cells in the IQ down cell stream. The OBC has to provide a valid cell header without HEC, followed by at least six bytes and at most the complete cell payload (a total of 52 octets). The HEC is generated when transmitted onto the IQ interface.

Interfacing between the OBC and the downstream cell stream is performed by the same cell FIFO buffer as for the upstream cell insertion. Also for downstream cell insertion, a back pressure mechanism is implemented. Cells received in the VC-4/SPE have a higher priority than cells from 10 the OBC. Synchronisation is performed by a synchronisation signal, which indicates to the cell i insertion device where the boundary between two inserted cells in the FIFO buffer is.

For cell extraction in the upstream direction, such is performed using the cell filtering •mechanism described above. Only the first four octets of the cell header and the complete payload are extracted from the IQ up interface. For interfacing between the extraction circuitry and the 15 OBC, a FIFO buffer is used. The OBC should synchronise to the extracted cell stream by reading blocks of 52 octets until the buffer is empty.

Downstream cell extraction is performed using the cell filtering mechanism mentioned above. Only the first four octets of the cell header and the complete payload are extracted from the VC-4/SPE. Before a possible extraction, the HEC in these cells is already checked for errors.

20 For interfacing between the extraction circuitry and the OBC, a FIFO buffer is used. The OBC should be synchronised to the extracted cell stream by reading blocks of 52 octets until the buffer is empty. The cell which is extracted towards the OBC can optionally be sent to the IQ down interface also.

As suggested above, the IQ down and IQ up buses transport ATM cells with a five-octet header and a 48octet information field. In front of each cell is one dummy octet, illustrated in Figure 14H. The ATM cells are encapsulated in 54 octet slots and provided access to the IQ bus.

The adaptation of 155.52 Mbit/s to 152.64 Mbit/s (53/54*155.52 Mbit/s) is performed by the deletion of idle cells. This can be done due to the fact that the maximum bit rate of valid ATM cells contained in the VC4s/SPEs is limited to 149.76 Mbit/s (26-27* 155.52 Mbit/s).

The dummy octet is added to the ATM cells in order to allow a changeover from one LT to another on the IQ up interface (between cells). On the IQ down interface, this octet is not filled in, on the IQ up interface, the bus is in high impedance state during this octet.

004061512v7.doc 26 The NT card is managed by an ADS workstation (AWS) which may be located in an operating system (OS) as shown in Figure 5. Such an OS may communicate through an ATM network and an ATM switch in a central office with the NT card in the shelf. See copending and co-owned U.S. patent application SIN (Atty. Docket No. 907-160) entitled "ASAM Network Management System with Open Loop Flow Control", filed on even date herewith for further details, and which is hereby incorporated by reference. Figure 14C shows a front view and Figure 14D a side view of an NT card, such as may be used in a slot of a shelf of Figure 1.

Figure 14E shows a more detailed functional block diagram of an NT card 12a of Figure 1. An optical/electrical transceiver provides a SONET/SDH 10 compliant interface for 155.52 Mbps STM1 or STS3-c signals in one integrated package. Clock recovery is done in the S/UNI+. In order to do this clock recovery, it requires a reference clock.

The recovered clock (155.52 MHz) is divided by eight in the S/UNI+ and serves as one of the inputs for serving as a reference clock to a PLL circuit located in a UIAC block to which a VCXO output clock must track (if loop timing is enabled). The resulting clock out of the VCXO serves 15 as input clock for transmit data towards the optical transceiver, where this clock is used to synthesise the transmit clock, and which also serves as a system clock. The reference clock input and the VCXO output clock are further divided by a factor N in the UIAC (N 2048 for Bellcore and N 128 for ITU). After a phase comparison between the two resulting divided clocks, the resulting voltage is fed to a lowpass filter, after which the signal drives the VCXO. Loop timing 20 can be established by locking the transmit clock (system clock) on the receive clock.

At the ATM side of the S/UNI+ there are two internal four-cell synchronous FIFO's present that are controlled by the UIAC. This interface acts as an SCI/PHY (Utopialike) interface.

Back pressure (upstream) is inherently present due to the FIFOfs integrated in the S/UNI. For the upstream direction, this means that if there is a full load of 155.52 Mbps on the IQ bus (152.64 Mbps at the Utopia interface) and a maximum transmit capacity of 149.76 Mbps ATM cells, the four-cell FIFO will be full after 1.5 ms.

The UIAC component is an LCA device which is programmed during "power-on-reset" from a serial PROM. It uses three synchronous 512 x 9 bit FIFOs for cell insertion and extraction and one 128K x 8 bit SRAM for routing. The UIAC module has a SCI/PHY (Utopia-like) interface to the S/UNI+ component. ATM cell insertion in both the direction of the network (SDH/SONET) and in the direction of the LTs is handled by a 1 SIF (signalling insertion FIFO) buffer. An OBC bus is connected directly to the eight data 004061512v7.doc 27 inputs of the FIFO. The direction of cell insertion is specified by the OBC by writing into an additional UIAC register. The ninth bit of the FIFO is used for cell synchronisation and insertion direction specification. A RAM lookup table is used for cell filtering on VPIJVCI combinations.

The RAM has 128K entries of eight bits.

Downstream cell extraction is performed by a downstream signalling extraction PIFO (DSEF). The eightbit output data of this buffer is connected to a peripheral bus. All cells which are extracted are copied by default to the downstream traffic stream. This can be disabled, however, by a traffic control register in the UIAC.

Upstream cell extraction is performed via the USEF (upstream signal extraction FIFO).

10 The eight-bit output data of this buffer is connected to the peripheral bus. A cell received on the upstream IQ interface is sent either to the OBC or to the upstream SDH/SONET interface. All cells which are extracted are copied by default to the upstream traffic stream. This can be disabled, however,' by the traffic control register in the UIAC.

In the downstream direction, ATM cells are transferred to an ICOM interface. In the 15 upstream direction, ATM cells are received from the ICOM.

The UIAC may be equipped by a boundary scan interface conforming to IEEE 1149.1 (JTAG) Specification.

A block diagram of an ADS Alarm Control Unit (ACU) is shown in Figure 15A, while the functions thereof are listed the table of Figure 15B. Figure 16 shows a front view and Figure S.i 20 17 a side view of the ACU.

Claims (19)

1. Network termination equipment for use in a shelf of a telecommunications system, said network termination equipment for connection to an asynchronous transfer mode (ATM) network and to a plurality of line termination equipment also for use in said shelf for connection to subscriber equipment, said network termination equipment including: physical medium termination equipment for interfacing to a physical medium by means of a serial input/output connection to said ATM network for providing a parallel input/output; transmission conveyance means connected to said parallel input/output for recovering/mapping ATM cells from/to frames of a transport format of said serial input/output; 10 ATM layer processing means connected to said transmission conveyance means for layer S processing downstream ATM cells recovered by said transmission conveyance means and for providing upstream ATM cells to said transmission conveyance means; and :an ATM bus interface responsive to downstream ATM cells from said ATM layer processing means for providing said downstream ATM cells with a guard byte for an ATM bus 15 in said shelf and responsive to upstream ATM cells with a guard byte for providing said upstream cells to said ATM layer processing means without said guard byte.

2. The network termination equipment of claim 1, wherein said physical medium termination equipment includes an optical interface.

The network termination equipment of either claim 1 or claim 2, wherein said physical 20 medium termination equipment includes means for locking onto a received downstream clock signal and means for providing a transmit clock in an upstream direction.

4. The network termination equipment of any one of claims 1 to 3, wherein said transmission conveyance means includes frame alignment recovery means for use in a downstream direction and frame generation means for use in an upstream direction.

5. The network termination equipment of claim 4, wherein said transmission conveyance means further includes descrambling/scrambling means for descrambling/scrambling STM1/STS3c signals.

6. The network termination equipment of any one of claims 1 to 5, wherein said ATM layer processing means includes ATM cell extraction/insertion means, ATM cell header error control checking and ATM layer processing plus cell rate decoupling.

7. Network termination equipment, for connection to an asynchronous transfer mode (ATM) network, said network termination equipment including: 004061512v7.doc 29 physical medium termination equipment for interfacing to a physical medium by means of a serial input/output connection to said ATM network for providing a parallel input/output; transmission conveyance means connected to said parallel input/output for recovering/mapping ATM cells from/to frames of a transport format of said serial input/output; ATM layer processing means connected to said transmission conveyance means for layer processing downstream ATM cells recovered by said transmission conveyance means and for providing upstream ATM cells to said transmission conveyance means; and an ATM bus interface responsive to downstream ATM cells from said ATM layer processing means for providing said downstream ATM cells with a guard byte for an ATM bus 10 in said shelf and responsive to upstream ATM cells with a guard byte for providing said upstream cells to said ATM layer processing means without said guard byte.

8. The network termination equipment of claim 7, wherein said physical medium termination equipment includes an optical interface.

9. The network termination equipment of either claim 7 or 8, wherein said physical 15 medium termination equipment includes means for locking onto a received downstream clock signal and means for providing a transmit clock in an upstream direction.

10. The network termination equipment of any one of claims 7 to 9, wherein said transmission conveyance means includes frame alignment recovery means for use in a downstream direction and frame generation means for use in an upstream direction. i 20

11. The network termination equipment of claim 10, wherein said transmission conveyance means further includes descrambling/scrambling means for descrambling/scrambling STM1/STS3c signals.

12. The network termination equipment of any one of claims 7 to 11, wherein said ATM layer processing means includes ATM cell extraction/insertion means, ATM cell header error control checking and ATM layer processing plus cell rate decoupling.

13. Network termination equipment for use in a shelf of a telecommunication system, said network termination equipment for connection to an asynchronous transfer mode (ATM) network, said network termination equipment including: physical medium termination equipment for interfacing to a physical medium by means of a serial input/output connection to said ATM network for providing a parallel input/output; transmission conveyance means connected to said parallel input/output for recovering/mapping ATM cells from/to frames of a transport format of said serial input/output; 004061512v7.doc ATM layer processing means connected to said transmission conveyance means for layer processing downstream ATM cells recovered by said transmission conveyance means and for providing upstream ATM cells to said transmission conveyance means; and an ATM bus interface responsive to downstream ATM cells from said ATM layer processing means for providing said downstream ATM cells with a guard byte for an ATM bus in said shelf and responsive to upstream ATM cells with a guard byte for providing said upstream cells to said ATM layer processing means without said guard byte.

14. The network termination equipment of claim 13, wherein said physical medium termination equipment includes an optical interface. 10

15. The network termination equipment of either claim 13 or 14, wherein said physical medium termination equipment includes means for locking onto a received downstream clock signal and means for providing a transmit clock in an upstream direction.

16. The network termination equipment of any one of claims 13 to 15, wherein said transmission conveyance means includes frame alignment recovery means for use in a i 15 downstream direction and frame generation means for use in an upstream direction.

17. The network termination equipment of claim 16, wherein said transmission conveyance means further includes descrambling/scrambling means for descrambling/scrambling STM1/STS3c signals.

18. The network termination equipment of any one of claims 13 to 17, wherein said ATM i 20 layer processing means includes ATM cell extraction/insertion means, ATM cell header error control checking and ATM layer processing plus cell rate decoupling.

19. Network termination equipment substantially as hereinbefore described with reference to the accompanying drawings. Dated this 25th day of March 2002 ALCATEL By its attorneys Freehills Carter Smith Beadle