AU2233099A - Trace based instruction caching - Google Patents

Trace based instruction caching

Info

Publication number
AU2233099A
AU2233099A AU22330/99A AU2233099A AU2233099A AU 2233099 A AU2233099 A AU 2233099A AU 22330/99 A AU22330/99 A AU 22330/99A AU 2233099 A AU2233099 A AU 2233099A AU 2233099 A AU2233099 A AU 2233099A
Authority
AU
Australia
Prior art keywords
based instruction
trace based
instruction caching
caching
trace
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU22330/99A
Other languages
English (en)
Inventor
Glenn J Hinton
Robert F Krick
Chan W Lee
David J. Sager
Michael D. Upton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2233099A publication Critical patent/AU2233099A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
AU22330/99A 1997-10-23 1999-01-15 Trace based instruction caching Abandoned AU2233099A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/956,375 US6018786A (en) 1997-10-23 1997-10-23 Trace based instruction caching
PCT/US1999/000959 WO2000042502A1 (en) 1997-10-23 1999-01-15 Trace based instruction caching

Publications (1)

Publication Number Publication Date
AU2233099A true AU2233099A (en) 2000-08-01

Family

ID=26795369

Family Applications (1)

Application Number Title Priority Date Filing Date
AU22330/99A Abandoned AU2233099A (en) 1997-10-23 1999-01-15 Trace based instruction caching

Country Status (6)

Country Link
US (1) US6018786A (enExample)
EP (1) EP1198747A4 (enExample)
JP (1) JP2003509733A (enExample)
CN (1) CN1169045C (enExample)
AU (1) AU2233099A (enExample)
WO (1) WO2000042502A1 (enExample)

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US6513155B1 (en) * 1997-12-12 2003-01-28 International Business Machines Corporation Method and system for merging event-based data and sampled data into postprocessed trace output
US6216206B1 (en) * 1997-12-16 2001-04-10 Intel Corporation Trace victim cache
US6105081A (en) * 1998-06-01 2000-08-15 Advanced Micro Devices, Inc. UART character matching used for address matching on a register-by-register basis
US6339822B1 (en) 1998-10-02 2002-01-15 Advanced Micro Devices, Inc. Using padded instructions in a block-oriented cache
US6442674B1 (en) * 1998-12-30 2002-08-27 Intel Corporation Method and system for bypassing a fill buffer located along a first instruction path
US6185669B1 (en) * 1999-02-18 2001-02-06 Hewlett-Packard Company System for fetching mapped branch target instructions of optimized code placed into a trace memory
US8234099B2 (en) * 1999-10-15 2012-07-31 Hemopet Computer program for determining a nutritional diet product for a canine or feline animal
US7548839B2 (en) * 1999-10-15 2009-06-16 Hemopet System for animal health diagnosis
WO2001028415A1 (en) 1999-10-15 2001-04-26 Dodds W Jean Animal health diagnosis
US6730023B1 (en) * 1999-10-15 2004-05-04 Hemopet Animal genetic and health profile database management
US6594734B1 (en) * 1999-12-20 2003-07-15 Intel Corporation Method and apparatus for self modifying code detection using a translation lookaside buffer
US6578138B1 (en) 1999-12-30 2003-06-10 Intel Corporation System and method for unrolling loops in a trace cache
US7260684B2 (en) * 2001-01-16 2007-08-21 Intel Corporation Trace cache filtering
US6950924B2 (en) * 2002-01-02 2005-09-27 Intel Corporation Passing decoded instructions to both trace cache building engine and allocation module operating in trace cache or decoder reading state
US20030191893A1 (en) * 2002-04-09 2003-10-09 Miller John Alan Method, system, and apparatus for efficient trace cache
US7941651B1 (en) 2002-06-27 2011-05-10 Intel Corporation Method and apparatus for combining micro-operations to process immediate data
US7010665B1 (en) 2002-06-27 2006-03-07 Intel Corporation Method and apparatus for decompressing relative addresses
US7103751B1 (en) 2002-06-27 2006-09-05 Intel Corporation Method and apparatus for representation of an address in canonical form
US7111148B1 (en) 2002-06-27 2006-09-19 Intel Corporation Method and apparatus for compressing relative addresses
US7124277B2 (en) * 2003-08-22 2006-10-17 Intel Corporation Method and apparatus for a trace cache trace-end predictor
US7133969B2 (en) * 2003-10-01 2006-11-07 Advanced Micro Devices, Inc. System and method for handling exceptional instructions in a trace cache based processor
US8069336B2 (en) * 2003-12-03 2011-11-29 Globalfoundries Inc. Transitioning from instruction cache to trace cache on label boundaries
US20050149709A1 (en) * 2003-12-29 2005-07-07 Intel Corporation Prediction based indexed trace cache
US7457917B2 (en) * 2004-12-29 2008-11-25 Intel Corporation Reducing power consumption in a sequential cache
US7239980B2 (en) * 2005-08-30 2007-07-03 International Business Machines Corporation Method and apparatus for adaptive tracing with different processor frequencies
US8015359B1 (en) * 2005-09-28 2011-09-06 Oracle America, Inc. Method and system for utilizing a common structure for trace verification and maintaining coherency in an instruction processing circuit
US8024522B1 (en) 2005-09-28 2011-09-20 Oracle America, Inc. Memory ordering queue/versioning cache circuit
US8037285B1 (en) 2005-09-28 2011-10-11 Oracle America, Inc. Trace unit
US8019944B1 (en) 2005-09-28 2011-09-13 Oracle America, Inc. Checking for a memory ordering violation after a speculative cache write
US8370576B1 (en) 2005-09-28 2013-02-05 Oracle America, Inc. Cache rollback acceleration via a bank based versioning cache ciruit
US8499293B1 (en) 2005-09-28 2013-07-30 Oracle America, Inc. Symbolic renaming optimization of a trace
US7783863B1 (en) 2005-09-28 2010-08-24 Oracle America, Inc. Graceful degradation in a trace-based processor
US7814298B1 (en) 2005-09-28 2010-10-12 Oracle America, Inc. Promoting and appending traces in an instruction processing circuit based upon a bias value
US7877630B1 (en) 2005-09-28 2011-01-25 Oracle America, Inc. Trace based rollback of a speculatively updated cache
US7606975B1 (en) 2005-09-28 2009-10-20 Sun Microsystems, Inc. Trace cache for efficient self-modifying code processing
US7949854B1 (en) 2005-09-28 2011-05-24 Oracle America, Inc. Trace unit with a trace builder
US7937564B1 (en) 2005-09-28 2011-05-03 Oracle America, Inc. Emit vector optimization of a trace
US7966479B1 (en) 2005-09-28 2011-06-21 Oracle America, Inc. Concurrent vs. low power branch prediction
US7747822B1 (en) 2005-10-31 2010-06-29 Oracle America Inc. Maintaining memory coherency with a trace cache
US7987342B1 (en) 2005-09-28 2011-07-26 Oracle America, Inc. Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer
US8032710B1 (en) 2005-09-28 2011-10-04 Oracle America, Inc. System and method for ensuring coherency in trace execution
US8051247B1 (en) 2005-09-28 2011-11-01 Oracle America, Inc. Trace based deallocation of entries in a versioning cache circuit
US7849292B1 (en) 2005-09-28 2010-12-07 Oracle America, Inc. Flag optimization of a trace
US7587585B1 (en) 2005-10-26 2009-09-08 Sun Microsystems, Inc. Flag management in processors enabled for speculative execution of micro-operation traces
US7953933B1 (en) 2005-09-28 2011-05-31 Oracle America, Inc. Instruction cache, decoder circuit, basic block cache circuit and multi-block cache circuit
US7953961B1 (en) 2005-09-28 2011-05-31 Oracle America, Inc. Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder
US7779307B1 (en) 2005-09-28 2010-08-17 Oracle America, Inc. Memory ordering queue tightly coupled with a versioning cache circuit
US7870369B1 (en) 2005-09-28 2011-01-11 Oracle America, Inc. Abort prioritization in a trace-based processor
US7681019B1 (en) 2005-11-18 2010-03-16 Sun Microsystems, Inc. Executing functions determined via a collection of operations from translated instructions
US7797517B1 (en) 2005-11-18 2010-09-14 Oracle America, Inc. Trace optimization via fusing operations of a target architecture operation set
US20070186049A1 (en) * 2006-02-03 2007-08-09 International Business Machines Corporation Self prefetching L2 cache mechanism for instruction lines
US20080215804A1 (en) * 2006-09-25 2008-09-04 Davis Gordon T Structure for register renaming in a microprocessor
US20080077778A1 (en) * 2006-09-25 2008-03-27 Davis Gordon T Method and Apparatus for Register Renaming in a Microprocessor
US8370609B1 (en) 2006-09-27 2013-02-05 Oracle America, Inc. Data cache rollbacks for failed speculative traces with memory operations
US8010745B1 (en) 2006-09-27 2011-08-30 Oracle America, Inc. Rolling back a speculative update of a non-modifiable cache line
US8386712B2 (en) * 2006-10-04 2013-02-26 International Business Machines Corporation Structure for supporting simultaneous storage of trace and standard cache lines
US7644233B2 (en) * 2006-10-04 2010-01-05 International Business Machines Corporation Apparatus and method for supporting simultaneous storage of trace and standard cache lines
US7610449B2 (en) * 2006-10-04 2009-10-27 International Business Machines Corporation Apparatus and method for saving power in a trace cache
US20080250206A1 (en) * 2006-10-05 2008-10-09 Davis Gordon T Structure for using branch prediction heuristics for determination of trace formation readiness
US7934081B2 (en) * 2006-10-05 2011-04-26 International Business Machines Corporation Apparatus and method for using branch prediction heuristics for determination of trace formation readiness
US20080250207A1 (en) * 2006-11-14 2008-10-09 Davis Gordon T Design structure for cache maintenance
US20080114964A1 (en) * 2006-11-14 2008-05-15 Davis Gordon T Apparatus and Method for Cache Maintenance
US20080120468A1 (en) * 2006-11-21 2008-05-22 Davis Gordon T Instruction Cache Trace Formation
US20080235500A1 (en) * 2006-11-21 2008-09-25 Davis Gordon T Structure for instruction cache trace formation
US8181005B2 (en) * 2008-09-05 2012-05-15 Advanced Micro Devices, Inc. Hybrid branch prediction device with sparse and dense prediction caches
US8012769B2 (en) * 2008-11-12 2011-09-06 Hemopet Thyroid analyte detection and measurement
US7799532B2 (en) * 2008-11-12 2010-09-21 Hemopet Detection and measurement of thyroid hormone autoantibodies
US7794954B2 (en) * 2008-11-12 2010-09-14 Hemopet Detection and measurement of thyroid analyte profile
US20100151062A1 (en) * 2008-12-16 2010-06-17 Bruno Stefanon Determining nutrients for animals through gene expression
US7873482B2 (en) * 2008-12-16 2011-01-18 Bruno Stefanon Diagnostic system for selecting nutrition and pharmacological products for animals
KR20100084036A (ko) * 2009-01-15 2010-07-23 삼성전자주식회사 소프트웨어의 에러 검출 장치 및 방법
US8621149B2 (en) * 2009-12-23 2013-12-31 Intel Corporation Controlling access to a cache memory using privilege level information
CN103513957B (zh) * 2012-06-27 2017-07-11 上海芯豪微电子有限公司 高性能缓存方法
CN103513958B (zh) * 2012-06-27 2017-01-25 上海芯豪微电子有限公司 高性能指令缓存系统和方法
CN102789483B (zh) * 2012-06-30 2014-12-10 华为技术有限公司 数据验证方法、装置和系统
US9442725B2 (en) * 2013-08-21 2016-09-13 Airwatch Llc Branch trace compression
US10606599B2 (en) * 2016-12-09 2020-03-31 Advanced Micro Devices, Inc. Operation cache
US9934127B1 (en) 2017-03-08 2018-04-03 Microsoft Technology Licensing, Llc Indexing a trace by insertion of key frames for replay responsiveness
US9983978B1 (en) 2017-03-08 2018-05-29 Microsoft Technology Licensing, Llc Querying an indexed time-travel trace
US9934126B1 (en) 2017-03-08 2018-04-03 Microsoft Technology Licensing, Llc Indexing a trace by insertion of reverse lookup data structures
US9940369B1 (en) 2017-03-08 2018-04-10 Microsoft Technology Licensing, Llc Searching an indexed time-travel trace
US10185645B2 (en) 2017-03-08 2019-01-22 Microsoft Technology Licensing, Llc Resource lifetime analysis using a time-travel trace
US9959194B1 (en) 2017-03-08 2018-05-01 Microsoft Technology Licensing, Llc Indexing a trace by insertion of memory snapshots for replay responsiveness
US10282274B2 (en) 2017-06-14 2019-05-07 Microsoft Technology Licensing, Llc Presenting differences between code entity invocations
CN110851073B (zh) * 2018-08-20 2023-06-02 慧荣科技股份有限公司 储存装置及巨集指令的执行方法
WO2020167303A1 (en) 2019-02-13 2020-08-20 Nokia Technologies Oy Programmable control of processor resources

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* Cited by examiner, † Cited by third party
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AU3776793A (en) * 1992-02-27 1993-09-13 Intel Corporation Dynamic flow instruction cache memory

Also Published As

Publication number Publication date
EP1198747A1 (en) 2002-04-24
JP2003509733A (ja) 2003-03-11
EP1198747A4 (en) 2005-03-16
US6018786A (en) 2000-01-25
CN1354852A (zh) 2002-06-19
WO2000042502A1 (en) 2000-07-20
CN1169045C (zh) 2004-09-29

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase