AU2022322054A1 - A charge-locking circuit and method - Google Patents

Abstract

A charge-locking circuit has a first multiplexer for selectively connecting an input to each one of a plurality of outputs. Each output is electrically isolated from all other outputs. Each output comprises a recharging capacitance arranged to be charged to a voltage applied to the input when the respective output is connected to the input through the first multiplexer. Each recharging capacitance is arranged to ret ain that voltage until the output is connected to a holding capacitance. The charge -locking circuit also has at least one holding capacitance provided for each output, each holding capacitance is connectable to its respective output and disconnectable from its respective output.

Description

A CHARGE-LOCKING CIRCUIT AND METHOD FIELD OF THE INVENTION The present invention relates to a circuit for implementing charge-locking, and to a method of operating a charge-locking circuit. BACKGROUND Many classical and quantum technologies require multiple control and signal lines from room temperature to a cryogenic environment. As the number of individual devices increases, there is a problem of depleting resources, such as cooling power and physical space, if each device is individually connected. This is especially a problem if non-uniformity of individual devices limits the extent to which common control voltages can be used. An example of such a technology is a semiconductor spin qubit based on a gate-defined quantum dot (QD) device. It may require numerous gates to define the necessary potential landscape for one QD, and the voltage on each gate requires precise tuning to operate the QD. When scaled up to many such devices, a large number of individually tunable voltages have to be simultaneously maintained, which poses a significant problem. One conventional approach to address this situation is to employ charge - locking circuitry to provide individual tunability. One example of charge locking circuitry is illustrated in Figure 1, and comprises a multiplexer (MUX) and an array of charge-locking units. Each charge-locking unit 10 is made up of a capacitor Cj and a switch (illustrated as a transistor). A voltage at the terminal 12 of the MUX can be selectively connected to any one of the MUX output lines to operate the selected switch (in this trivial example, the MUX is a 2-level, base-2, MUX, so there are four output lines; further details of MUX operation will be explained below). In cha rge- locking unit 10, when the switch is ON, the capacitor is charged up to a static voltage V_hold applied to the horizontal control line 14, and can hold that voltage for a period of time when the switch is set to the OFF state. The voltage on the capacitor of each charge-locking unit is then present at the respective output (0, 1, 2, 3), and can be applied to tune the desired device(s). Each charge-locking unit can be set to a different voltage. To maintain the correct output voltage level, each capacitor has to be periodically recharged. Figure 1 shows a 1D array of charge-locking units, and can in principle be extended to charge-lock a large number of DC signals. The same principle can be extended to a 2D array of charge-locking units, as shown in Figure 2. In this case, each charge-locking unit comprises two transistor switches in series; one transistor can be switched on/off by a row control line, and the other transistor can be switched on/off by a column contro l line. As a result, each combination of a row control line and a column control line corresponds to one charge-locking unit, and the addressing is like a conventional cross -bar array. In this way, an array of M × N charge-locking units can be controlled by just M + N control lines. For controlling large arrays, the row and column lines need to be multiplexed (as in Figure 1) to further reduce the total number of physical control lines. The use of multiplexers and/or cross-bar addressing reduces the number of control lines/wires required, and so reduces the thermal conduction path to the cryogenic environment. However, power must still be dissipated to periodically recharge the charge-locking units. Three contributions to the total power dissipation come from: moving charge to refresh the voltage on the capacitors; driving the switches of the charge-locking units; and power dissipated in any MUX. For a 1D array as in Figure 1, the power dissipated becomes dominated by the power dissipated in the MUX, and grows quadratically with the total number of charge-locking units. For a 2D array implemented with conventional cross-bar addressing approach (Figure 2), the power dissipated also shows superlinear dependence (to the power of 3/2) on the total number of charge-locking units (regardless of the precise implementation, and even if row and column MUXs are used). This power dissipation presents a problem as arrays of charge -locking units become ever larger, such as hundreds, thousands or even millions o f charge-locking units, such as for a large-scale quantum circuit, when the total cooling power available may be only 1 mW at a temperature of 100 mK for large dilution fridges, and when thermal noise must be carefully limited to avoid disturbing delicate quantum states. Furthermore, the total recharging time required for periodically recharging a conventional charge-locking circuit array presents another problem that can limit the maximum size of the charge-locking circuit. The present invention aims to alleviate, at least partially, some or any of the above problems. SUMMARY According to one aspect of the invention there is provided a charge-locking circuit, comprising: a first multiplexer having an input and a plurality of outputs, wherein the input is selectively connectable to each output, and wherein each output is electrically isolated from all other outputs, wherein each output comprises a recharging capacitance arranged to be charged to the voltage of the input when connected to the input, and to retain that voltage until the output is connected to a holding capacitance; and at least one holding capacitance provided for each output, each holding capacitance being connectable to its respective output and disconnectable from its respective output. Another aspect of the invention provides a method of operating a charge - locking circuit that comprises: a first multiplexer having an input and a plurality of outputs, wherein the input is selectively connectable to each output, and wherein each output is electrically isolated from all other outputs, wherein each output comprises a recharging capacitance arranged to be charged to the voltage of the input when connected to the input, and to retain that voltage until the output is connected to a holding capacitance; and at least one holding capacitance provided for each output, each holding capacitance being connectable to its respective output and disconnectable from its respective output, the method comprising: connecting the input to one output to charge the recharging capacitance at the one output to a predetermined voltage applied to the input; isolating the one output from the input; repeating the connecting and isolating steps separately for each output to provide a respective voltage at each output; simultaneously, for all outputs, connecting a respective holding capacitance associated with each output to its respective output to transfer charge between the recharging capacitance of the output and the respective holding capacitance; and disconnecting all holding capacitances from the outputs of the multiplexer to lock the charge on the holding capacitances. Further optional aspects of the invention are defined in the dependent claims . Embodiments of the invention enable charge-locking units to be periodically recharged row-wise in a parallel manner, rather than performing periodic recharging serially; consequently, the number of switchings required is reduced and hence the power consumption is reduced. It can be shown that for a parallel recharged (refreshed) 1D array, embodiments of the invention enable a reduction in the rate of energy dissipation of the circuit. For example, for a charge-locking circuit consisting of ~1000 charge- locking units, and with relatively large transistors of size 1 µm × 1.4 µm (transistor gate capacitance 14 fF), the dissipation can be as low as 150 nW per kHz refreshing frequency. The rate of energy dissipation is also about 400 times lower than the equivalent conventional serial 1D charge-locking circuit, which dissipates about 60 µW/kHz. It can also be shown that for a parallel recharged (refreshed) 2D array, embodiments of the invention enable very close to linear growth in the rate of energy dissipation as the size of the array scales up. For example, for a charge -locking circuit consisting of ~10⁶ charge-locking units, (e.g. 1024×1024 array), and with transistors of size 14 nm × 10 nm, the dissipation can be as low as 35 nW/kHz. This also represents a 400 times reduction in the rate of energy dissipation compared with the conventional cross-bar 2D array which dissipates about 14 µW/kHz. Improvement in the uniformity of the QD device characteristics (such a gate- voltage variation) will lead to a further reduction in the rate of energy dissipation, for example decreasing to 22 nW/kHz in the previous example if the voltage variation is reduced to 10 mV. This reduction is absent in the conventional approaches. According to some models, it is considered that of the order of 100 million (10⁸) qubits may be the threshold number of qubits required for running error correction code in a fault-tolerant quantum computing device. For 2¹⁴×2¹⁴ charge- locking units (i.e. ~2.6×10⁸ charge-locking units), and a transistor gate of 10 nm × 14 nm (gate capacitance ~1.4 × 10⁻³ fF), with a serially refreshed charge- locking approach with conventional 2D cross-bar addressing, the power dissipation to maintain those charge-locking units is around 61.5 mW per kHz refreshing rate. In contrast, a parallel refreshed charge-locking solution according to an embodiment of the invention only dissipates 11 µW per kHz refreshing rate, which is a more than 5000 times reduction in power dissipation (under the same assumptions about the device, and with a gate voltage variation of ~100 mV). If the gate voltage variation is reduced to ~10 mV, the power dissipation can be further reduced to around 7.5 µW per kHz refreshing rate. Assuming a charge refreshing rate of 1 kHz, the power dissipation of a parallel refreshing approach according to an embodiment of the invention is only 11 µW, which consumes just more than 1% the 1 mW cooling power available at 100mK, leaving sufficient cooling power for other local electronics. In contrast, the power dissipation of conventional 2D addressing is 61.5 mW, more than 60 times the available cooling power at 100 mK. Embodiments of the invention can also have the advantage of a reduction in the total time required to perform periodic recharging of the charge -locking circuit. The total recharging time is another critical aspect that can limit the array size (number of charge-locking units in a charge-locking circuit). BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the invention will now be described, by way of non -limiting example, with reference to the accompanying drawings. The invention may further comprise, in any combination, any features of the embodiments which will now be described. Figure 1 is a schematic circuit diagram of a conventional 1D charge-locking circuit; Figure 2 is a schematic circuit diagram of a conventional 2D charge-locking array; Figure 3 is a schematic plan view of a 2-level base-2 MLSG MUX suitable for use with embodiments of the invention; Figure 4 is a schematic cross-section of a portion of the MUX of Figure 3; Figure 5 is a schematic circuit diagram of a MUX for use with embodiments of the invention; Figure 6 is a schematic circuit diagram of a 1D charge-locking circuit according to an embodiment of the invention; Figure 7 is a schematic circuit diagram of a 2D charge-locking circuit according to an embodiment of the invention; Figures 8(a) to 8(e) illustrate a sequence of operation of a MUX to charge the recharging capacitors at the outputs to respective individual voltages according to an embodiment of the invention; Figures 9(a) to 9(c) illustrate a sequence of operation of a charge-locking circuit to recharge a row of holding capacitors in parallel and set the holding capacitors into a charge-locked state according to an embodiment of the invention ; and Figure 10 is a schematic illustration of a 1-level base-4 MLSG MUX suitable for use with embodiments of the invention. In the drawings, like parts are indicated with like reference numerals, and, for conciseness, description thereof will not be repeated. DETAILED DESCRIPTION An example of multiplexer (MUX) technology, known as multiple level selective gating (MLSG), suitable for use in embodiments is illustrated in Figures 3 and 4. Figure 3 shows a MUX in plan-view, comprising an input terminal 20 joined by a conductive channel 22 to a plurality of output terminals lab elled 0-3, all provided on a substrate 24. The channel 22 splits into multiple branches, firstly splitting into two branches, and then each of those branches splitting in two, to give four branches for the four outputs 0-3. Each stage at which there is a splitting or division of the channel is known as a level, so this example is a 2-level MUX because there are two levels of splitting. The number of branches into which each channel at the present level splits into at the next level is the ‘base’ of the multiplexing; so the example MUX of Figure 3 is base-2 because each splitting is a bifurcation. Overall, Figure 3 shows a 2-level base-2 MUX. This is purely one example, and other different numbers of levels and bases are contemplated, including not all l evels in the MUX being the same base. At each level of the MUX, following the splitting of the channel, gates are provided so that each new channel can be turned on or off depending on the voltage applied to the gates, hence the phrase ‘multiple level selective gating’ (MLSG). In Figure 3, the first level is provided with two gates 1R, 1L, and the second level is provided with two gates 2R, 2L. One physical implementation of the MUX and gating arrangement is illustrated in Figure 4, which shows a schematic cross-section (not to scale) of the device of Figure 3 taken along a portion of the length of the gate 1R. A semiconductor structure containing a conductive layer, such as a 2-dimensional electron gas (2DEG), is fabricated on the substrate 24. This structure is then wet-etched to leave the path of the conductional channels 22 as an unetched mesa on the substrate 24 (Figures 3 and 4). A thin insulating layer 26, such as Al₂O₃, is then deposited over the entire device. A layer of further spacing insulator 28, such as 500 nm of polyimide, is then provided on top, except for particular regions where some of the gates are to pass over the mesa of the channel 22. Patterned gate metallization 30 (such as Ti/Au) is then formed on top of the structure for all of the gates 1R, 1L, 2R, 2L, and ohmic contacts are formed to the channel at the input terminal 20 and output terminals 0 -3. Where the gate metal passes over the channel (shown as the darker region 32 in Figure 4) without any intervening polyimide, applying a negative gate voltage (such as −0.6 V) can switch off conduction of the channel 22. In contrast, to switch off conduction in the channel 22 on the left of Figure 4, where the gate is spaced apart from the channel mesa by the polyimide layer, requires a gate voltage in the region of −7.0 V. So, activating the gate 1R with a voltage of say −1 V stops conduction in the right-hand channel, but does not affect conduction in the left -hand channel. Referring to Figure 3, the dark rectangles schematically illustrate where the gates bridge over the channel 22 with a thick insulating layer (e.g. polyimide), such that the channel is not affected by small gate voltages (in practice the polyimide can be provided over practically the entire substrate). All other locations where a gate crosses a channel are provided with a window in the insulating polyimide such that the gate is in close proximity to the channel (as shown for region 32 in figure 4). Thus, activating gate 1R can turn off the right-hand conduction channel; and activating gate 1L can turn off the left-hand conduction channel. Gates 2L and 2R can be activated to turn off respective alternate (even/odd) channels at the second level. In subsequent circuit diagrams, gates are shown schematically as rectangles; a solid rectangle indicates a gate is activated (ON) to block a channel (non-conductive), and an open rectangle indicates the gate is de-activated (OFF) such that the channel is conductive. For examples of the operation of the MUX in Figure 3: output 0 is selected by activating gates 1R and 2R (to block the channels to all other outputs); and output 1 is selected by activating gates 1R and 2L. Charge-locking circuits embodying the invention will now be described. Figure 5 shows a circuit diagram of a 2-level base-2 MLSG MUX. This will be referred to as first MUX 40. The first MUX 40 can be constructed like the device of Figure 3 (or any other suitable multiplexer construction), however, in addition, each multiplexed output is connected to a capacitor, referred to as a recharging capacitor C_Rj (j = 0, 1, 2, 3). The input 20 can be connected to each of the outputs separately and the respective recharging capacitor can be charged to whatever voltage is applied to the input 20. For example, with the state of the gates as shown in Figure 5, the input 20 is connected to output 0 with recharging capacitor C_R0. By switching the gates (as discussed further below) and changing the voltage applied to the input 20, each of the recharging capacitors can be charged to a different desired voltage. Figure 6 shows a 1D array charge-locking circuit comprising the first MUX 40 of Figure 5 with each multiplexed output 0-3 connected to a respective holding capacitor C_Hj (j = 0, 1, 2, 3) via switches 42 (e.g. transistors) that are controlled by a shared control line GH. By applying a suitable control voltage (or gate voltage) to the control line GH, all the holding capacitors C_Hj can be simultaneously connected to the first MUX 40 for recharging from the recharging capacitors CRj in the MUX 40; and then the control voltage can be changed (or removed) to disconnect all the holding capacitors C_Hj from the first MUX 40 for isolating their static voltages (charge-locked voltages). The voltages on the holding capacitors are applied (via outputs, such as output 44) to the particular device (not shown) being tuned. To extend to a 2D charge-locking array, more rows of holding capacitors C_Hij are added, as shown in Figure 7. Connection of each row of holding capacitors C_Hij is controlled by a respective control line GHi, and the control lines are controlled by a second MUX 50 (the second MUX 50 can be identical to the first MUX 40, except that it does not require the recharging capacitors C_Rj). All the holding capacitors in one column of the 2D array share the same output of the first MUX 40, and are selectably connectable to the first MUX 40 by the respective row control line GH. A sequence of operation of the first MUX 40 and charge-locking circuit will now be described with reference to Figures 8 and 9. Firstly, gates 1R and 2R are activated (see Figure 3), and a voltage V0 applied to the input 20 of the MUX; this situation is shown schematically in Figure 8(a). MUX output 0 is connected to the input 20, and recharging capacitor C_R0 is charged to V₀. As can be seen in Figure 8(a), all the other recharging capacitors are isolated from the input 20 and from the C_R0. Next, gate 1L is activated and gate 1R is de-activated, as shown in Figure 8(b). This disconnects recharging capacitor C_R0 from the input 20, and instead selects output 2. The input voltage is set to V₂ to charge up recharging capacitor C_R2, while the static voltage on C_R0 at output 0 stays unchanged. Thereafter, gate 2L is activated and gate 2R is de-activated, which disconnects capacitors C_R0 and C_R2 from the input 20, and selects output 3, as shown in Figure 8(c). The input is then set to V₃ to charge recharging capacitor C_R3. Next, addressing gate 1R is activated and gate 1L is de- activated, which disconnects capacitor C_R3 from the input 20, and instead selects output 1 (Figure 8(d)). The input is then set to V₁ to charge recharging capacitor C_R1. Lastly, gate 2R is activated to isolate capacitors C_R1 and C_R3; gate 1R can also optionally be de-activated, and this results in the state shown in Figure 8(e), in which four recharging capacitors C_R0 – C_R3 have each been charged to hold a different static voltage V₀ – V₃. Figure 9(a) shows the MUX of Figure 8(e) with its outputs connected to a row of holding capacitors C_H00 – C_H03. This could be a single row of a 1D array, such as Figure 6, or one row for illustrative purposes from a 2D array, such as Figure 7. Initially, all holding capacitors are kept in a charge -locked state (by the transistors controlled by the control line GH₀ being turned OFF) while the recharging capacitors are prepared to hold the right voltages for recharging (per Figures 8(a)-8(e)). Then the transistors are turned ON by the shared control line GH₀ to connect respective recharging capacitors and holding capacitors (Figure 9(b)) such that charge redistributes among the recharging capacitors and holding capacitors to recharge the holding capacitors. The transistors are then turned OFF by the control line GH₀ such that all of the holding capacitors C_H00-C_H03 are set into the charge-locked state (Figure 9(c)). The process can then be repeated to prepare the recharging capacitors to another set of voltages, and then turning ON a different row of transistors via a different control line GH_i, to recharge another row of holding capacitors C_Hi0 – C_Hi3 (Figure 7) and so on to recharge a whole array of holding capacitors in a charge - locking circuit, row by row. Each holding capacitor can be recharged to a static voltage that can be different from all the other voltages in the array . The above procedure is for the periodic recharging (also referred to as ‘refreshing’) of the voltage on the holding capacitors C_H; the voltage drifts because of leakage currents. To initialize the voltages on the holding capacitors, the procedure of Figure 8 of setting the recharging capacitors can be performed while one of the shared control lines GH_i turns one row of transistors on (Figure 9(b)), such that the row of holding capacitors is simultaneously charged as each respective recharging capacitor is charged from the MUX input 20. The control line GH_i then turns off that row of transistors. These steps are then repeated to initialize each row of holding capacitors. Regarding the size of the holding capacitors C_H in an embodiment of the invention, the voltage resolution (i.e. precision with which the voltage locked on the capacitor can be set) is determined by the larger of the charge discreteness e/C_H or the thermal noise level For cryogenic applications, to reach a voltage resolution of 1 µV at a temperature of 100 mK, holding capacitor C_H has to be at least 1.4 pF, which is set by the thermal noise. Such a holding capacitor can be fabricated with dimensions of 14 µm × 10 µm (e.g. using currently available planar technology having an upper limit of 10 fF/µm²). It can be shown that, because of charge discreteness, the capacitance of the recharging capacitor does not need to be larger than the capacitance of the holding capacitor. Indeed, for a 2D charge-locking array, it is preferable that the capacitance of any recharging capacitor C_R be much smaller than that of the corresponding holding capacitor C_H, to reduce power dissipation; for example, a suitable C_R might be 0.01C_H or smaller, such as 10⁻³ C_H. In this description and corresponding drawings, the capacitors are shown as discrete components, but that is not essential; what is required is an electrical capacitance for storing charge to maintain a voltage, whether this capacitance is provided by a discrete capacitor, multiple capacitors, by some component providing the equivalent function to a capacitor, by a distributed capacitance, or by other examples. So, the term ‘capacitance’ is a generalization of a discrete ‘capacitor’ component, and a ‘capacitor’ is merely one example of a component for providing such capacitance. Regarding the sequence of operating the addressing gates (switches) of the first MUX 40 in embodiments of the invention, this can be done in a specific way such that connecting one recharging capacitor C_R for charging will simultaneously maintain all the previously charged recharging capacitors as disconnected (isolated). So, as illustrated in the simple example Figure 8, the method does not charge the recharging capacitors sequentially: C_R0, C_R1, C_R2, C_R3. Instead the gates are operated in a way, as will be explained, that reduces the total number of switchings, reduces power dissipation, and maintains the set voltage of all the previously charged recharging capacitors by keeping them disconnected. Figure 8 illustrated the gate-switching sequence for a 2-level base-2 MLSG MUX. This can be extended to a base-2 MUX of more levels, for example consider a 4-level base-2 MUX; each level has two gates, ‘L’ and ‘R’ (as shown in Figure 3, but extended to more levels). Table 1 shows a gate-switching sequence to individually charge a recharging capacitor at each of the sixteen MUX outputs (numbered 0−15 from left to right). In the table, the activated state of a gate is labelled as ON, and the de-activated state of a gate is labelled as OFF. The relationship between the selected output and the state of the addressing gates is easily revealed in binary representation: at each level, and activated L addressing gate corresponds to ‘1’ and an activated R addressing gate corresponds to ‘0’. For example, output 11 is selected by activating 1L/2R/3L/4L, which corresponds to 1011 in binary and is equal to 11 in decimal . TABLE 1 From this addressing gate switching pattern, it is evident that gates of higher level are switched less frequently (in the example of Table 1, gates 4L and 4R are switched only once each). The higher-level gates have large gate capacitance (e.g. as can be seen in Figure 3, gate 2R switches two channels, but gate 1R switches only one channel – the regions where the gate metal is close to the channel for switching purposes are regions of high capacitance). The larger gate capacitance means th at more charge must flow to change the voltage to effect switching; therefore, the less frequent switching of the higher-level (higher capacitance) gates, means less charge must flow and therefore there is less energy dissipation in operating the MUX, particularly in comparison with the conventional case where the outputs are selected , for example either sequentially in numerical order 0, 1, 2,…15 , or in an arbitrary order. In the conventional approach, to recharge any arbitrary capacitor, one addressing gate at each level will be switched on/off once; hence a higher level gate is switched as frequently as a lower level gate, leading to greater energy dissipation. Below we generalise the approach to operate a MLSG based MUX as the Column MUX for parallel refreshed charge-locking. The MUX can be either of homogenous base (e.g. Table 2) or heterogenous base (e.g. Table 3). For a MLSG based MUX of K level, the total number of output channels N is equal to the product of the base of each level. That is

, where B_i is the base of ith level i.e. at ith level each channel from (i — 1)th level is split into B_i channels. Physically, it means there are B_i addressing gates at ith level. The output channel O is labelled from 0 to N-1, and each can be uniquely mapped into a K-bit sequence representing the inactive addressing gate of each level. That is

, where the ith bit α_i is in the range of [0, 1, ..., B_i — 1]. More specifically,

, where W_i is the weight of the ith bit and is equal to

It can be verified that the above correspondence is reduced into the mapping between binary number and decimal number for homogenous base-2 MUX.

We now describe the specific sequence to charge-lock static voltages at each output, of which the addressing gates of higher level are switched less frequently, thereby reducing the power dissipation.

1) Start with output channel each 1^st level addressing gate is set to inactive state once in ascending order to charge-lock voltage at the corresponding output channel i.e. in sequence.

2) Changing the inactive addressing gate of 2^nd level from 0 to 1. Upon this transition output channels are kept in charge-locked state by activated addressing gate 0 of 2^nd level and simultaneously allow output channels ^st to be selected by 1 level addressing gates. From set each 1^st level addressing gate to inactive state once in descending order to charge-lock voltage at the corresponding output channel, i.e. in sequence.

3) Repeat procedure 2) for each 2^nd level addressing gate being set to inactive once in ascending order, i.e. group of output channels to be set into charge-locked state in sequence, within each group of output channels the 1^st level addressing gate are scanned in alternating ascending/descending order.

4) Once all the output channels are set into charge-locked state following the above procedure. To proceed, changing the inactive addressing gate of 3^rd level from 0 to 1, which keeps all the output channels in charge-locked state meanwhile allow to be selected by 2 ^nd and 1^st level addressing gates. For B₂ being even, the transition occurs between , while for B₂ being odd, the transition occurs between

5) Same as alternating the order of scanning 1 ^st level addressing gate once the 2^nd level addressing gate is changed. Now the 2^nd level addressing gate is scanned in descending order, which allows group of output channels to be set into charge-locked state in sequence. Again, within each group of output channels, the 1 ^st level addressing gate are scanned in alternating ascending/descending order.

6) Repeat procedure 5) for each 3^rd level addressing gate being set to inactive once in ascending order, while the order of scanning 2^nd and 1^st level addressing gate are alternated accordingly. All the output channels can be set into charge-locked state.

7) Following the same idea, we can iterate through higher level addressing gates until output channel is set to charge-locked state.

Two examples of switching sequences following this procedure are given in Table 2 and Table 3 respectively. Table 2 shows the sequence to operate a 3-level base-3 MUX and Table 3 shows the sequence to operate a 3-level heterogenous base MUX (1^st level base 2, 2^nd level base 5 and 3^rd level base 3). TABLE 2 Table 2 shows a sequence to operate a 3-level base-3 MUX for parallel refreshed charge-locking. Inactive addressing gates are labelled as OFF and active addressing gates are labelled as ON. For MUX of homogenous base, there is a simple correspondence between the output channel an d the inactive addressing gates. For example, 23 corresponds to 212 that is 23 = 2×3² + 1×3¹ + 2×3⁰. Physically this means all addressing gates other than gate 2 of level 1, gate 1 of level 2 and gate 2 of level 3 are activated to select output channel 23. Upon the transition from 18 to 21, 2nd level inactive addressing gate is changed from 0 to 1. The activated addressing gate 0 of 2nd level keeps output channel 0, 9, 18 or equivalently 000, 100, 200 in charge -locked state. Upon the transition from 24 to 25, 3rd level inactive addressing is changed from 0 to 1. The activated addressing gate 0 of 3rd level keeps output channel 0, 9, 18, 21, 12, 3, 6, 15, 24 or equivalently 000, 100, 200 210, 110, 010, 020, 120, 220 in charge-locked state. TABLE 3 Table 3 shows a sequence to operate a 3-level MUX of heterogenous base (1st level of base 2, 2nd level of base 5, and 3rd level of base 3) for parallel refreshed charge- locking. Inactive addressing gates are labelled as OFF and active addressing gates are labelled as ON. There is a one to one correspondence between the inactive addressing gates and the output channel. For example, output channel 26 is selected for charging by activating all addressing gates other than gate 1 of 1st level, gate 3 of 2nd level and gate 2 of 3rd level, that is 26 = 1×(3×5) + 3×3 + 1×2. Upon the transition from 15 to 18, 2nd level inactive addressing gate is changed from 0 to 1. The activated addressing gate 0 of 2nd level keeps output channel 0, 15 or equivalently 000, 100 in charge-locked state. Upon the transition from 27 to 28, 3rd level inactive addressing is changed from 0 to 1. The activated addressing gate 0 of 3rd level keeps output channel 0, 15, 18, 3, 6, 21, 24, 9, 12 or equivalently 000, 100, 110 010, 020, 120, 130, 030, 040, 140 in charge-locked state. So, in a generalized method for operating the MLSG MUX to minimize energy dissipation, each process of isolating one output from the input and connecting the input to the next output, comprises performing switching at only one level of the MUX, and in particular at that level, one gate is changed from de -activated to activated (OFF to ON) and one gate is changed from activated to de -activated (ON to OFF). Preferably, the all the gates at the lowest level (1^st level) are cycled through in sequence to be the deactivated one; then the deactivated gate at the next lowest level (2^nd level) is changed, followed by repeating the cycling at the lowest level again. This is repeated until all the gates at the 2^nd level have been the deactivated one in sequence; then the deactivated gate at the 3^rd level is changed. This whole nested process is iterated (as can be seen most clearly in the examples of Tables 2 and 3) until all of the outputs have been selected, with the further preferred feature that the sequence of repeatedly cycling through the gates at a particular level alternates direction (for example, in Table 2, at the 2^nd level, the de-activated gate sequence progresses 0, 1, 2, then 2, 1, 0, then 0, 1, 2). Although described above with reference to the column MUX, or first MUX 40, the same efficient switching sequence can also be employed for the second MUX 50 (row MUX). In embodiments of the invention, the terms ‘column’ and ‘row’ can be interchanged, and indeed ‘column’ and ‘row’ are merely labels for the two dimensions of a 2D array, and do not imply any particular orientation such as horizontal or vertical. As illustrated in Tables 2 and 3, there is no particular limit to the ‘base’ at any particular level of the MUX (the ‘base’ being the number of branches into which each channel from the next lowest level splits). Only base-4 is as efficient as base-2; bases larger than base-4 will be less efficient in terms of scaling up the number of multiplexed outputs. However, embodiments of the invention can in general lead to further reduction in power dissipation for any bases used in the MUX. Figure 3 showed an implementation of base-2 multiplexing. Figure 10 shows an example of how to implement base-4 multiplexing in MLSG: activating gate 1A will block conduction in the channel leading to output 0 (but does not affect the other outputs); de-activating gate 1A connects the input 20 to the output 0. Similarly , for gates 1B, 1C and 1D regarding outputs 1, 2 and 3, respectively. Of course, there can be multiple parallel structures like Figure 10 at higher levels of the MUX, all sharing the same four gate lines for that level. The general principle in MLSG is that the number of gates at any level is equal to the base at that level, and in operation, just one of the gates at that level is de-activated (OFF) at any given time. For a level that is base-2, with two gates, during operation, one gate will be OFF and the other gate ON, so they are the complement of each other; this could be controlled by a single signal line and a local inverter. Similarly, for the base-4 situation, the four gates could be controlled by two signal lines (two bits, giving four values) with local circuitry to control the four gates from the two signal lines. The general principle can be extended to any number of gates. However, it is generally simpler to have one signal line for each gate, and the extra thermal conduction of the signal lines, if coming from a warm environment to the MUX in a cryogenic environment, is off-set by not requiring local circuitry to control the addressing gates. As an example, to operate a 2D array of 1 million charge-locking units, requires only 42 lines supplied from higher temperature: 20 for the addressing gates of each MUX (assuming each MUX is 10-level base-2, giving 1024×1024 array), and 1 line for the input of each MUX. Similarly, for ~2.6 × 10⁸ charge-locking units (2¹⁴×2¹⁴ array), in principle only 58 lines fed from higher temperature are required; 28 lines for the addressing gates of each MUX and 1 line for the input of each MUX. One other aspect of embodiments of the invention is the reduction in recharging time for the circuit. The minimum acceptable recharging frequency is determined by the leakage current and the allowed static voltage drift. The time required to recharge all the charge-locking units in the circuit sets the upper limit for the recharging frequency (and so sets an upper limit on the total number of units that can be maintained). With a 2D array charge-locking circuit according to an embodiment of the invention, the recharging time is reduced by a factor of roughly C_H/C_R (the ratio of the holding capacitance to the recharging capacitance) as compared with the conventional approach. So, for example, for C_R set to 10⁻³C_H for reduced power dissipation, this also results in a 1000 times reduction in total recharging time , effectively increasing the upper limit for charge-locking array size by the same ratio.

Claims (13)

1. CLAIMS 1. A charge-locking circuit, comprising: a first multiplexer having an input and a plurality of outputs, wherein the input is selectively connectable to each output, and wherein each output is electrically isolated from all other outputs, wherein each output comprises a recharging capacitance arranged to be charged to the vol tage of the input when connected to the input, and to retain that voltage until the output is connected to a holding capacitance; and at least one holding capacitance provided for each output, each holding capacitance being connectable to its respective output and disconnectable from its respective output.
2. 2. A circuit according to claim 1, wherein all of the outputs are simultaneously connectable to a respective holding capacitance associated with each output, and simultaneously disconnectable from the respective holding capacitance.
3. 3. A circuit according to claim 2, wherein each output is selectively connectable to each of a plurality of holding capacitances.
4. 4. A circuit according to any preceding claim, comprising a 2D array of holding capacitances.
5. 5. A circuit according to claim 4, wherein each output is provided with a respective column of holding capacitances, and is selectively connectable to any capacitance in said column.
6. 6. A circuit according to claim 5, further comprising a second multiplexer, each output of the second multiplexer being connected to a control line arranged to control the connection and isolation of one row of holding capacitances to the respective outputs of the first multiplexer.
7. 7. A circuit according to any preceding claim, wherein the first multiplexer comprises conduction channels and multiple level selective gates to control the conduction channels.
8. 8. A circuit according to any preceding claim, wherein the charge -locking circuit is a cryogenic charge-locking circuit.
9. 9. A circuit according to any preceding claim, wherein the number of holding capacitances is at least 1000.
10. 10. A method of operating a charge-locking circuit that comprises: a first multiplexer having an input and a plurality of outputs, wherein the input is selectively connectable to each output, and wherein each output is electrically isolated from all other outputs, wherein each output comprises a recharging capacitance arranged to be charged to the voltage of the input when con nected to the input, and to retain that voltage until the output is connected to a holding capacitance; and at least one holding capacitance provided for each output, each holding capacitance being connectable to its respective output and disconnectable from its respective output, the method comprising: connecting the input to one output to charge the recharg ing capacitance at the one output to a predetermined voltage applied to the input; isolating the one output from the input; repeating the connecting and isolating steps separately for each output to provide a respective voltage at each output; simultaneously, for all outputs, connecting a respective holding capacitance associated with each output to its respective output to transfer charge between the recharging capacitance of the output and the respective holding capacitance; and disconnecting all holding capacitances from the outputs of the multiplexer to lock the charge on the holding capacitances.
11. 11. A method according to claim 10, further comprising: repeating all the steps of claim 10 a plurality of times, using a different row of holding capacitances each time.
12. 12. A method according to claim 11, comprising controlling a second multiplexer to select a different row of holding capacitances to be charged each time.
13. 13. A method according to claim 10, 11 or 12, wherein the first multiple xer comprises a plurality of levels of splitting the input, wherein the process of isolating one output from the input and connecting the input to the next output comprises performing switching at only one level of the first multiplexer.