AU2021106414A4 - An uart-spi protocol bridge - Google Patents
An uart-spi protocol bridge Download PDFInfo
- Publication number
- AU2021106414A4 AU2021106414A4 AU2021106414A AU2021106414A AU2021106414A4 AU 2021106414 A4 AU2021106414 A4 AU 2021106414A4 AU 2021106414 A AU2021106414 A AU 2021106414A AU 2021106414 A AU2021106414 A AU 2021106414A AU 2021106414 A4 AU2021106414 A4 AU 2021106414A4
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- AU
- Australia
- Prior art keywords
- uart
- spi
- interface
- bridge
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 230000002093 peripheral effect Effects 0.000 claims description 6
- 230000003111 delayed effect Effects 0.000 claims description 4
- 238000011161 development Methods 0.000 claims description 3
- 230000000630 rising effect Effects 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 2
- 238000004891 communication Methods 0.000 abstract description 19
- 230000005540 biological transmission Effects 0.000 abstract description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
Abstract
AN UART-SPI PROTOCOL BRIDGE
The present invention relates to an UART-SPI protocol bridge. The object of the
proposed invention is to provide an interface module which enables us to interface SPI
device to get directly interfaced with PC through UART. It's enables and creates a
protocol bridge between these two protocols which carried out data transmission and
communication serially. It also opens the gate where we can have multiple SPI device
communicating through a single UART interface found in controller. This aims in
making the transmission and reception of data faster and easier. It will enable definitely
enable many devices to interact amongst themselves.
Description
Technical field of invention:
The present invention relates to the field of electronics and telecommunication engineering and more specifically to an interface module which enables user to interface SPI device to get directly interfaced with PC through UART.
Background of the present invention
The background information herein below relates to the present disclosure but is not necessarily prior art.
Serial communication interfaces are widely used in touch controllers, microcontrollers, peripheral devices, baseband application processor or system-on-chip (SOC) applications, etc. A number of serial communication protocols can be used for communicating over serial communication interfaces. As an example, inter integrated circuit (12C), system management bus (SMBus), two wire interface (TWI), serial peripheral interface (SPI), or universal synchronous and asynchronous receiver and transmitter (USART) are serial communication protocols that may be used for communication through serial communication interfaces.
There are multiple ways to establish communication link between a device and PC i.e. via parallel port, serial port, ethernet port and as such many other links are also possible. Also there are a lot of devices available, which follow serial communication, but they are unable to communicate directly to PC, since standard PC interface does not follow these serial communication interface (like 12C, SPI and many others).
The universal asynchronous receiver transmitter (UART) interface and the serial peripheral interface (SPI) both enable serial communication between the MSP430 microcontroller (MCU) and another devices, such as a personal computer (PC) or another MCU or processor. UART is asynchronous in nature and handles the data synchronization and transmission through start bits and stop bits without the help of a CLK and whereas SPI is synchronous and has CLK for data synchronization, so many devices may only be able to communicate by one or the other of them.
Some designs require communication between devices with these different serial protocols. This can be done using a bridge to convert packets from one protocol to the other.
Thus there is need to develop and introduce a protocol bridge for effective and fast data communications. Hence the present invention provides an UART SPI protocol bridge which enable communication between devices efficiently.
Objective of the invention:
The primary object of the present invention is to provide a protocol bridge between UART and SPI, two serial communication protocols.
Another object of the present invention is to provide an interface module which enables user to interface SPI device to get directly interfaced with PC through UART.
Yet another object of the present invention is to provide with the interoperability which will ease the data communication in between the protocols and make it faster, better and more convenient.
Summary of the invention
Accordingly present invention provides an UART-SPI protocol bridge. The proposed invention provides an interface module which enables user to interface SPI device to get directly interfaced with PC through UART. For implementation of the UART-to-SPI bridge, the MSP-TS430PW20 target development board has been used for connecting the peripherals to the MSP430FR2000 MCU. Ensured that jumpers JP14 and JP15 are populated (leave JP13 unpopulated), jumper J16 is set to UART, and jumpers JP11, JP17 and JP18 are all removed. These jumper settings allow the backchannel UART interface on the MSP-FET programmer and debugger to simulate the UART device that will be communicating with the bridge. Using jumper wires connect J4.14 (P2.0) to JP11.3 and connect J4.13 (P2.1) to JP11.4. To connect to a SPI device, connect the SPI device's clock pin to J4.17 (P1.5), the MOSI pin to J4.16 (P1.6), the MOSI pin to J4.15 (P1.7), and GND to J2.2. The UART to SPI bridge functions as a SPI master in 3 wire mode. Low polarity is used, and the phase is 0 (TX data is shifted out on the rising clock edge).
Detailed description of invention
The present invention relates to an UART-SPI protocol bridge. The proposed invention provide an interface module which enables user to interface SPI device to get directly interfaced with PC through UART.
In the preferred embodiment, for implementation of the UART-to-SPI bridge, the MSP-TS430PW20 target development board has been used for connecting the peripherals to the MSP430FR2000 MCU. Ensured that jumpers JP14 and JP15 are populated (leave JP13 unpopulated), jumper J16 is set to UART, and jumpers JP11, JP17 and JP18 are all removed. These jumper settings allow the backchannel UART interface on the MSP-FET programmer and debugger to simulate the UART device that will be communicating with the bridge.
Using jumper wires connect J4.14 (P2.0) to JP11.3 and connect J4.13 (P2.1) to JP11.4. To connect to a SPI device, connect the SPI device's clock pin to J4.17 (P1.5), the MOSI pin to J4.16 (Pl.6), the MOSI pin to J4.15 (Pl.7), and GND to J2.2. The UART to SPI bridge functions as a SPI master in 3-wire mode. Low polarity is used, and the phase is 0 (TX data is shifted out on the rising clock edge).
In the proposed invention, communication must be initiated by the UART device because the UART-to-SPI bridge is configured as a SPI master. This could be changed by configuring the bridge as a SPI slave and connecting it to a SPI master, which could then initiate the communication.
For the firmware implementation, the main code initializes the digitally controlled oscillator (DCO), the hardware and software UART pins, the eUSCI SPI module, and the Timer module. Then, the central processing unit (CPU) goes to sleep by entering low power mode 0 (LPMO). When the MCU receives UART or SPI interrupts, the CPU wakes up, enters active mode, and transmits the received data as quickly as possible before going back to sleep.
When a SPI packet is received on the MOSI pin (Pl.6), the UCRXIFG interrupt flag is set, and the data bits are read from the SPI RX buffer. Next, the Timer module is started and delayed repeatedly to send the start bit, then each of the eight data bits, and then the stop bit over the software UART transmit pin (P2.0).
The software UART receive pin (P2.1) is initially configured as a general purpose input-output (GPIO) that provides an interrupt on the falling edge of an input signal. When a UART packet is received by P2.1, the falling edge of the start bit triggers this interrupt flag. Next, the Timer module is started and delayed repeatedly to read each of the eight data bits. The data bits are placed in the SPI TX buffer and sent over the SPI MOSI pin (P1.7).
The firmware supports half-duplex UART communication only, which means one direction at a time. It also supports UART packets with eight data bits, least significant bit (LSB) first, no parity bit, and one stop bit. Because two serial interfaces are required, and the MSP430FR2000 MCU has one eUSCI module, the UART interface is implemented in software using the Timer module.
To change the baud rate of the software UART interface, user can change the WHOLEBIT definition in the code, which equals the subsystem master clock (SMCLK) divided by the baud rate. The HALFBIT definition is just half this value. The SMCLK operates at 16 MHz. The SPI interface is operating with a bit clock equal to half of SMCLK. The SPI device needs to be taken into account when setting the bit clock rate on the UART-to-SPI bridge.
The many features and advantages of the invention are apparent from the detailed specification, and thus, it is intended by the appended claims to cover all such features and advantages of the invention which fall within the true spirit and scope of the invention. Further, since numerous modifications and variations will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation illustrated and described, and accordingly, all suitable modifications and equivalents may be resorted to, falling within the scope of the invention.
Claims (3)
1. An UART-SPI protocol bridge provides an interface module which enables user to interface SPI device to get directly interfaced with PC through UART, characterize in that; for implementation MSP-TS430PW20 target development board used for connecting the peripherals to MSP430FR2000 MCU; ensured that jumpers JP14 and JP15 are populated (leave JP13 unpopulated), jumper J16 is set to UART and jumpers JP11, JP17 and JP18 are all removed; these jumper settings allow the backchannel UART interface on the MSP-FET programmer and debugger to simulate the UART device that will be communicating with the bridge; using jumper wires connect J4.14 (P2.0) to JP11.3 and connect J4.13 (P2.1) to JP11.4; to connect to a SPI device connect the SPI device's clock pin to J4.17 (P.5), the MOSI pin to J4.16 (P1.6), the MOSI pin to J4.15 (P1.7), and GND to J2.2; the UART to SPI bridge functions as a SPI master in 3-wire mode,low polarity is used and the phase is 0 (TX data is shifted out on the rising clock edge).
2. An UART-SPI protocol bridge as claimed in claim 1 wherein for the firmware implementation the main code initializes the digitally controlled oscillator (DCO), the hardware and software UART pins, the eUSCI SPI module and the Timer module; thenthe central processing unit (CPU) goes to sleep by entering low power mode 0 (LPMO); when the MCU receives UART or SPI interrupts the CPU wakes up, enters active mode, and transmits the received data as quickly as possible before going back to sleep; when a SPI packet is received on the MOSI pin (P1.6), the UCRXIFG interrupt flag is set and the data bits are read from the SPI RX buffer; next the Timer module is started and delayed repeatedly to send the start bit then each of the eight data bits and then the stop bit over the software UART transmit pin (P2.0).
3. An UART-SPI protocol bridge as claimed in claim 1 wherein when a UART packet is received by P2.1, the falling edge of the start bit triggers this interrupt flag and timer module is started and delayed repeatedly to read each of the eight data bits which are placed in the SPI TX buffer and sent over the SPI MOSI pin (P1.7).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AU2021106414A AU2021106414A4 (en) | 2021-08-22 | 2021-08-22 | An uart-spi protocol bridge |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AU2021106414A AU2021106414A4 (en) | 2021-08-22 | 2021-08-22 | An uart-spi protocol bridge |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| AU2021106414A4 true AU2021106414A4 (en) | 2021-12-02 |
Family
ID=78716520
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU2021106414A Ceased AU2021106414A4 (en) | 2021-08-22 | 2021-08-22 | An uart-spi protocol bridge |
Country Status (1)
| Country | Link |
|---|---|
| AU (1) | AU2021106414A4 (en) |
-
2021
- 2021-08-22 AU AU2021106414A patent/AU2021106414A4/en not_active Ceased
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| FGI | Letters patent sealed or granted (innovation patent) | ||
| MK22 | Patent ceased section 143a(d), or expired - non payment of renewal fee or expiry |