AU2017309892B2 - Rate matching for block encoding - Google Patents

Rate matching for block encoding Download PDF

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Publication number
AU2017309892B2
AU2017309892B2 AU2017309892A AU2017309892A AU2017309892B2 AU 2017309892 B2 AU2017309892 B2 AU 2017309892B2 AU 2017309892 A AU2017309892 A AU 2017309892A AU 2017309892 A AU2017309892 A AU 2017309892A AU 2017309892 B2 AU2017309892 B2 AU 2017309892B2
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AU
Australia
Prior art keywords
block
block size
rate matching
code
circuit
Prior art date
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Active
Application number
AU2017309892A
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English (en)
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AU2017309892A1 (en
Inventor
Jilei Hou
Jian Li
Chao Wei
Changlong Xu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
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Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of AU2017309892A1 publication Critical patent/AU2017309892A1/en
Application granted granted Critical
Publication of AU2017309892B2 publication Critical patent/AU2017309892B2/en
Priority to AU2021286440A priority Critical patent/AU2021286440B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6356—Error control coding in combination with rate matching by repetition or insertion of dummy data, i.e. rate reduction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • H04L1/0013—Rate matching, e.g. puncturing or repetition of code symbols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/08—Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Error Detection And Correction (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
AU2017309892A 2016-08-10 2017-06-12 Rate matching for block encoding Active AU2017309892B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2021286440A AU2021286440B2 (en) 2016-08-10 2021-12-17 Rate matching for block encoding

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
AUPCT/CN2016/094374 2016-08-10
PCT/CN2016/094374 WO2018027669A1 (en) 2016-08-10 2016-08-10 Rate matching for block encoder
PCT/CN2017/087888 WO2018028294A1 (en) 2016-08-10 2017-06-12 Rate matching for block encoding

Related Child Applications (1)

Application Number Title Priority Date Filing Date
AU2021286440A Division AU2021286440B2 (en) 2016-08-10 2021-12-17 Rate matching for block encoding

Publications (2)

Publication Number Publication Date
AU2017309892A1 AU2017309892A1 (en) 2019-01-24
AU2017309892B2 true AU2017309892B2 (en) 2021-12-16

Family

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Family Applications (2)

Application Number Title Priority Date Filing Date
AU2017309892A Active AU2017309892B2 (en) 2016-08-10 2017-06-12 Rate matching for block encoding
AU2021286440A Active AU2021286440B2 (en) 2016-08-10 2021-12-17 Rate matching for block encoding

Family Applications After (1)

Application Number Title Priority Date Filing Date
AU2021286440A Active AU2021286440B2 (en) 2016-08-10 2021-12-17 Rate matching for block encoding

Country Status (7)

Country Link
US (2) US11218177B2 (enExample)
EP (2) EP3497791B1 (enExample)
JP (3) JP7304809B2 (enExample)
CN (1) CN109565288B (enExample)
AU (2) AU2017309892B2 (enExample)
CA (1) CA3029265C (enExample)
WO (2) WO2018027669A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018027669A1 (en) 2016-08-10 2018-02-15 Qualcomm Incorporated Rate matching for block encoder
WO2018106001A1 (ko) * 2016-12-06 2018-06-14 엘지전자 주식회사 폴라 코드를 이용한 제어 정보 전송 방법 및 장치
CN109889304B (zh) * 2017-01-05 2020-06-16 华为技术有限公司 速率匹配方法、编码装置和通信装置
CN109150376B (zh) * 2017-06-16 2022-02-15 大唐移动通信设备有限公司 一种信道编码方法及设备
KR102438982B1 (ko) * 2017-11-16 2022-09-01 삼성전자주식회사 무선 통신 시스템에서 부호화 및 복호화를 위한 방법 및 장치
CN108092742B (zh) * 2017-12-17 2019-11-22 华中科技大学 一种基于极化码的通信方法

Citations (1)

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CN101192878A (zh) * 2006-11-28 2008-06-04 华为技术有限公司 一种高速下行分组接入传输的控制方法、系统及装置

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DE10030407B4 (de) * 1999-07-14 2011-09-01 Lg Electronics Inc. Verfahren zur optimalen Ratenanpassung in einem Mobilkommunikationssystem
US6898743B2 (en) * 2000-07-03 2005-05-24 Lg Electronics Inc. Data rate matching method in 3GPP2 system
EP2293452B1 (en) * 2000-07-05 2012-06-06 LG ELectronics INC. Method of puncturing a turbo coded data block
US6973039B2 (en) * 2000-12-08 2005-12-06 Bbnt Solutions Llc Mechanism for performing energy-based routing in wireless networks
DE10129777A1 (de) * 2001-06-20 2003-01-02 Siemens Ag Verfahren und Vorrichtung zur Datenübertragung gemäß einem ARQ-Verfahren
US7372837B2 (en) * 2001-10-26 2008-05-13 Texas Instrument Incorporated Incremental redundancy using two stage rate matching for automatic repeat request to obtain high speed transmission
AU2005239657B2 (en) * 2004-12-01 2007-12-13 Samsung Electronics Co., Ltd. Method and apparatus for transmitting and receiving data with high reliability in a mobile communication system supporting packet data transmission
EP1826937A1 (en) * 2006-02-27 2007-08-29 STMicroelectronics S.r.l. Transmitter and receiver with efficient memory management in rate matching processes
CN101488833B (zh) * 2009-01-20 2011-07-06 北京天碁科技有限公司 一种用于td-scdma系统的上行信道编码方法和下行信道解码方法
US20120008555A1 (en) * 2010-06-23 2012-01-12 Qualcomm Incorporated Transmit and receive processing in the presence of interference in a wireless network
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Also Published As

Publication number Publication date
AU2017309892A1 (en) 2019-01-24
JP2023126812A (ja) 2023-09-12
AU2021286440B2 (en) 2023-07-06
CN109565288B (zh) 2023-04-28
EP3497791A4 (en) 2020-07-01
CA3029265C (en) 2023-09-26
US11218177B2 (en) 2022-01-04
WO2018028294A1 (en) 2018-02-15
CN109565288A (zh) 2019-04-02
US20220200634A1 (en) 2022-06-23
WO2018027669A1 (en) 2018-02-15
EP3713095A1 (en) 2020-09-23
US20190296776A1 (en) 2019-09-26
BR112019002063A2 (pt) 2019-05-07
JP2019527978A (ja) 2019-10-03
US11973518B2 (en) 2024-04-30
JP7304809B2 (ja) 2023-07-07
JP2022092030A (ja) 2022-06-21
EP3497791B1 (en) 2024-01-17
EP3497791A1 (en) 2019-06-19
CA3029265A1 (en) 2018-02-15
AU2021286440A1 (en) 2022-01-20
EP3497791C0 (en) 2024-01-17

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