AU2016380796B2 - Replay of partially executed instruction blocks in a processor-based system employing a block-atomic execution model - Google Patents

Replay of partially executed instruction blocks in a processor-based system employing a block-atomic execution model Download PDF

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Publication number
AU2016380796B2
AU2016380796B2 AU2016380796A AU2016380796A AU2016380796B2 AU 2016380796 B2 AU2016380796 B2 AU 2016380796B2 AU 2016380796 A AU2016380796 A AU 2016380796A AU 2016380796 A AU2016380796 A AU 2016380796A AU 2016380796 B2 AU2016380796 B2 AU 2016380796B2
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Prior art keywords
instruction
replay
record
block
instruction block
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AU2016380796A
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AU2016380796A1 (en
Inventor
Gregory Michael Wright
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3648—Debugging of software using additional hardware
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Retry When Errors Occur (AREA)
AU2016380796A 2015-12-28 2016-12-09 Replay of partially executed instruction blocks in a processor-based system employing a block-atomic execution model Active AU2016380796B2 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562271475P 2015-12-28 2015-12-28
US62/271,475 2015-12-28
US15/252,323 US11188336B2 (en) 2015-12-28 2016-08-31 Replay of partially executed instruction blocks in a processor-based system employing a block-atomic execution model
US15/252,323 2016-08-31
PCT/US2016/065740 WO2017116652A1 (en) 2015-12-28 2016-12-09 Replay of partially executed instruction blocks in a processor-based system employing a block-atomic execution model

Publications (2)

Publication Number Publication Date
AU2016380796A1 AU2016380796A1 (en) 2018-06-07
AU2016380796B2 true AU2016380796B2 (en) 2021-12-16

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AU2016380796A Active AU2016380796B2 (en) 2015-12-28 2016-12-09 Replay of partially executed instruction blocks in a processor-based system employing a block-atomic execution model

Country Status (8)

Country Link
US (1) US11188336B2 (OSRAM)
EP (1) EP3398060B1 (OSRAM)
JP (1) JP6963552B2 (OSRAM)
KR (1) KR102706938B1 (OSRAM)
CN (1) CN108369519B (OSRAM)
AU (1) AU2016380796B2 (OSRAM)
ES (1) ES2824474T3 (OSRAM)
WO (1) WO2017116652A1 (OSRAM)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10452516B2 (en) * 2017-07-10 2019-10-22 Microsoft Technology Licensing, Llc Replaying time-travel traces relying on processor undefined behavior
US10824429B2 (en) 2018-09-19 2020-11-03 Microsoft Technology Licensing, Llc Commit logic and precise exceptions in explicit dataflow graph execution architectures
US10983801B2 (en) * 2019-09-06 2021-04-20 Apple Inc. Load/store ordering violation management
US11360773B2 (en) * 2020-06-22 2022-06-14 Microsoft Technology Licensing, Llc Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5832202A (en) * 1988-12-28 1998-11-03 U.S. Philips Corporation Exception recovery in a data processing system

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EP0815507B1 (en) 1995-02-14 2013-06-12 Fujitsu Limited Structure and method for high-performance speculative execution processor providing special features
US6832367B1 (en) 2000-03-06 2004-12-14 International Business Machines Corporation Method and system for recording and replaying the execution of distributed java programs
FR2882449A1 (fr) * 2005-01-21 2006-08-25 Meiosys Soc Par Actions Simpli Procede non intrusif de rejeu d'evenements internes au sein d'un processus applicatif, et systeme mettant en oeuvre ce procede
US7882339B2 (en) 2005-06-23 2011-02-01 Intel Corporation Primitives to enhance thread-level speculation
US7506318B1 (en) 2005-06-28 2009-03-17 Replay Solutions, Inc. Recording and replaying computer programs
US8079019B2 (en) 2007-11-21 2011-12-13 Replay Solutions, Inc. Advancing and rewinding a replayed program execution
US7958497B1 (en) 2006-06-07 2011-06-07 Replay Solutions, Inc. State synchronization in recording and replaying computer programs
US8316352B2 (en) 2006-06-09 2012-11-20 Oracle America, Inc. Watchpoints on transactional variables
US8190859B2 (en) * 2006-11-13 2012-05-29 Intel Corporation Critical section detection and prediction mechanism for hardware lock elision
US8473919B2 (en) 2008-01-31 2013-06-25 Ca, Inc. System and method for repeating program flow for debugging and testing
JP5385545B2 (ja) * 2008-04-17 2014-01-08 インターナショナル・ビジネス・マシーンズ・コーポレーション トランザクションの実行を制御する装置及び方法
US8291202B2 (en) * 2008-08-08 2012-10-16 Qualcomm Incorporated Apparatus and methods for speculative interrupt vector prefetching
EP2996035A1 (en) 2008-10-15 2016-03-16 Hyperion Core, Inc. Data processing device
US8402318B2 (en) 2009-03-24 2013-03-19 The Trustees Of Columbia University In The City Of New York Systems and methods for recording and replaying application execution
US8549504B2 (en) 2010-09-25 2013-10-01 Intel Corporation Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic region
US8826273B1 (en) * 2010-12-22 2014-09-02 Vmware, Inc. Synchronously logging to disk for main-memory database systems through record and replay
US20130080738A1 (en) * 2011-09-23 2013-03-28 Qualcomm Incorporated Processor configured to perform transactional memory operations
US9170915B1 (en) 2011-12-06 2015-10-27 Amazon Technologies, Inc. Replay to reconstruct program state
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Also Published As

Publication number Publication date
WO2017116652A1 (en) 2017-07-06
EP3398060B1 (en) 2020-07-29
US11188336B2 (en) 2021-11-30
JP2018538628A (ja) 2018-12-27
KR102706938B1 (ko) 2024-09-12
CN108369519B (zh) 2022-03-01
BR112018012686A2 (pt) 2018-12-04
ES2824474T3 (es) 2021-05-12
EP3398060A1 (en) 2018-11-07
CN108369519A (zh) 2018-08-03
JP6963552B2 (ja) 2021-11-10
AU2016380796A1 (en) 2018-06-07
KR20180099680A (ko) 2018-09-05
US20170185408A1 (en) 2017-06-29

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