AU2016340016B2

AU2016340016B2 - A method and arrangement for controlling dimming to a lamp by a dimmer arrangement affected by ripple injection and/or superimposed supply authority ripple control signals upon the AC mains supply input wave signal

Info

Publication number: AU2016340016B2
Application number: AU2016340016A
Authority: AU
Inventors: Philip Tracy
Original assignee: Hendon Semiconductors Pty Ltd
Current assignee: Hendon Semiconductors Pty Ltd
Priority date: 2015-10-15
Filing date: 2016-10-14
Publication date: 2021-01-07
Anticipated expiration: 2036-10-14
Also published as: AU2016340016A1; WO2017063022A1; NZ742171A

Abstract

A method for controlling dimming of a dimmer arrangement to minimise effects of a ripple injection signal upon an AC mains supply input wave signal received by the dimer arrangement comprising: filtering a ripple injection signal from an AC mains supply input wave signal having said ripple injection signal superimposed thereon; inverting the filtered ripple injection signal; combining the inverted filtered ripple injection signal with the AC mains supply input wave signal having said ripple injection signal superimposed thereon to eliminate the ripple injection signal from the AC mains supply input wave signal to provide an AC mains supply wave signal from which a true zero crossing detection signal is derivable; wherein an input of the derived true zero crossing detection signal to a gate drive arrangement of the dimmer arrangement generates a timing reference signal to control an OFF or ON period for a load control arrangement of the dimmer arrangement, wherein said load control arrangement is adapted to turn OFF or ON the AC mains supply input wave signal having the ripple injection signal superimposed thereon to a lamp under the control of the dimmer arrangement for an ON or OFF period determined by the timing reference signal.

Description

A METHOD AND ARRANGEMENT FOR CONTROLLING DIMMING TO A LAMP BY

A DIMMER ARRANGEMENT AFFECTED BY RIPPLE INJECTION AND/OR SUPERIMPOSED SUPPLY AUTHORITY RIPPLE CONTROL SIGNALS UPON THE AC MAINS SUPPLY INPUT WAVE SIGNAL

TECHNOLOGICAL FIELD

[001] This invention relates to a method and arrangement for being able to generate a timing reference signal to control the supply of electrical power to a lamp under the control of a dimmer arrangement and more particularly to a timing reference signal to control the on/off period for electrical power to the lamp wherein the timing reference signal remains substantially unaffected by the AC mains supply input wave signal that has been coupled with a ripple injection signal and/or a superimposed supply authority ripple control signal.

BACKGROUND ART DISCUSSION

[002] Phase cutting dimmers operate by switching AC mains supply to the lamp or light load for only a chosen time portion of each AC mains supply half cycle. For the most part the objective is to maintain that timing as accurately and as stable as possible. Conventionally, the time period for which AC mains supply is applied to the load is determined by an analogue or digital timer, controlling the load switching device, that must be started and stopped at exact times during each AC mains supply half cycle.

[003] Two-wire trailing edge dimmers also referred to as reverse phase control dimmers remove power from the end or trailing edge of each AC mains supply cycle. These two terminal dimmers have replaced the conventional single pole light switches and for the most part are wired in series with the load and the time at which the timer is started and stopped, once again for the most part is derived by

processing the voltage that appears across the active and load dimmer voltage terminals. [004] In one simple form, the instant at which the dimmer terminal voltage falls to zero volts is used as the reference instant that stops and starts the timer wherein power is removed from the load.

[005] Nonetheless the addition of AC voltages to the AC mains supply frequencies, that allow supply authorities to remotely switch equipment, can cause variations in the instant at which the dimmer's terminal voltage will cross any particular voltage level, including zero volts. Consequently that in turn causes variations in the time that the dimmer applies the mains AC supply to the lamp or light load and results in modulation of the power delivered to the lamp or light and hence causes flickering and/or changes in lamp brightness.

[006] This ripple injection and/or superimposing of additional AC voltages to the AC mains supply are problematic to the effective dimming capabilities of the dimmer if it is going to appropriately be able to control the luminosity of the light or lamp over the dimming range without undesirable light intensity flickering. Therefore there is the requirement to reduce the modulating effects of those supply authority control signals referred to generally as "ripple control" signals, on the dimmer's control of the luminosity of the light to the relevant load.

[007] As the added or injected AC ripple frequencies are at frequencies higher than those of the AC mains supply frequency, dimmers may introduce low-pass filtering of the dimmer's voltage into the control circuitry in order to remove this unwanted injected ripple frequency interference.

[008] The prior art is full of patents that describe and claim for complex filtering means to regenerate a stable signal equivalent in time to the instant at which the AC mains supply frequency component of the terminal voltage, in the absence of any injected ripple frequency, would cross zero voltage.

[009] Nonetheless the problem with low-pass filtering is that it inherently introduces a time delay and may result in that the timing signal that is produced will only be available after the dimmer terminal voltage has actually crossed zero volts and therefore too late for use in trailing edge dimmers that require the timer provided by with the generated reference signal to be initialised or made available slightly before the dimmer terminal voltage crosses zero volts.

[010] Accordingly it is an object of this invention to be able to generate a timing reference signal to control the on/off period of the electrical power to the lamp under the control of the dimmer arrangement whereby that signal is generated without suffering the consequences of the excessive inherent delay one would expect from utilising low pass filtering techniques to remove the ripple injection from the AC mains supply input wave signal.

[01 1] A further object of this invention is to make the timing reference signal available prior to the next subsequent zero crossing thereby imposing no restriction on the lamp turn OFF time period thereby allowing for a minimum of zero for the lamp ON time previously considered unachievable when trying to provide for a stable timing reference signal to control the on/off period for a load under the control of a dimmer arrangement.

[012] Still further objects and advantages of this invention will become apparent from a complete reading of the following specification.

SUMMARY OF THE INVENTION

[013] In one form of the invention there is provided a method for controlling dimming of a dimmer arrangement to minimise the effects of a ripple injection signal upon an AC mains supply input wave signal received by the dimmer arrangement when controlling luminosity to a lamp under the control of the dimmer arrangement, said method including at least the steps of:

[014] filtering a ripple injection signal from an AC mains supply input wave signal having said ripple injection signal superimposed thereon said AC mains supply input wave signal; [015] phase shifting the filtered ripple injection signal180° to provide for an inverted filtered ripple injection signal;

[016] combining the inverted filtered ripple injection signal with the AC mains supply input wave signal having the ripple injection signal superimposed thereon, wherein the combining of the inverted filtered ripple injection signal with the AC mains supply input wave signal having the ripple injection signal superimposed thereon eliminates the ripple injection signal and generates an AC mains supply wave signal from which a true zero crossing detection signal is derivable;

[017] wherein the derived true zero crossing detection signal is generated prior to a subsequent true zero crossing at the dimmer arrangement voltage terminals of the AC mains supply input wave signal having the ripple injection signal superimposed thereon; and

[018] wherein an input of the derived true zero crossing detection signal to a gate drive arrangement generates a timing reference signal to control an OFF and/or ON period for a load control arrangement, wherein said load control arrangement is adapted to turn ON or OFF the AC mains supply input wave signal having the ripple injection signal superimposed thereon to a load under the control of the dimmer arrangement for the ON or OFF period determined by the timing reference signal.

[019] Advantageously while the AC mains supply input wave signal may have the ripple injection signal superimposed thereon the generated timing reference signal remains free from the effects of the superimposed ripple injection signal as the zero crossing detection signal was derived from a cleaned referenced signal resultant from the combining together of the inverted filtered ripple injection signal with the AC mains supply input wave signal having the ripple injection signal superimposed thereon which effectively achieved the elimination of the ripple injection signal from the AC mains supply. [020] In preference the gate drive arrangement includes a micro-processor wherein the input of the derived true zero crossing detection signal into the micro-processor generates a timing reference signal from the micro-processor.

[021] In preference the generated timing reference signal from the micro-processor is inputted into a signal amplifier with a low voltage supply, preferably the low voltage supply range of the signal amplifier is between 3.3V to 10 V.

[022] In preference the output from the signal amplifier controls an OFF and/or ON period for a load control arrangement.

[023] In preference the micro-processor receives the true zero crossing detection signal prior to a subsequent AC mains supply input wave signal true zero crossing whereupon availability of the true zero crossing detection signal prior to the next subsequent true zero crossing of the AC mains supply input wave signal places no restriction on the generatable timing reference signal to achieve load turn OFF immediately after the next true zero crossing of the AC mains supply input wave signal thereby permitting a minimum ON time for the load under the control of the dimmer arrangement.

[024] In preference the filtering and inverting of the ripple injection signal from the AC mains supply input wave signal having the ripple injection signal superimposed thereon includes an all pass filter.

[025] In preference the all pass filter includes two low pass filter functional blocks.

[026] In preference the all pass filter includes two low pass filter building blocks, wherein each low pass filter building blocks has a nominal cut off frequency set to equal the ripple injection signal to be removed.

[027] In an alternative form of the invention a high pass filter is used to filter the ripple injection signal from the AC mains supply input wave signal having the ripple injection signal superimposed thereon. [028] In preference the high pass filter is a third order filter.

[029] In preference the third order high pass filter includes a first capacitor, second capacitor and third capacitor wherein each of the first capacitor, second capacitor and third capacitor have a corresponding first resistor, second resistor or third resistor.

[030] In preference each stage of the third order high pass filter is arranged for a 60° phase shift of the ripple injection signal, so that the overall phase shift for the ripple injection signal is 180°.

[031] In preference a transistor is used to invert the overall 180°phase shifted ripple injection signal and a second transistor converts ripple signal voltage to a ripple signal current including a further inversion.

[032] In preference the load control arrangement for turning ON or OFF the AC mains supply wave input signal to the load includes a control switch with back-to- back Field Effect Transistors (FETs).

[033] In preference the FETs are N-channelled enhancement mode MOSFETs, with source terminals connected together with gates connected together and the drain terminals of each back-to-back FETs connected to a corresponding active terminal or load terminal.

[034] In preference each FET has an intrinsic body diode so as to allow conduction of current through the two wire trailing edge phase cutting dimmer arrangement in one direction.

[035] Advantageously utilising the unique filtering configurations as introduced above rather than a traditional low pass filtering technique allows for firstly the selective phase inversion of the ripple injection signal that was originally affecting the AC mains supply input wave signal and then once being able to invert the ripple injection signal it can then be added back into the AC mains supply wave input signal thereby subtracting the ripple injection frequency from the dimmer arrangement terminal voltage through simple cancellation.

[036] The filtering technique employed, whether it is through the use of the high pass filter or the all pass filter, has resulted in separating the ripple injection signal with significantly less delay of the AC mains but also importantly applying a phase shift so that this overall phase shift of 180° (inversion and/or complete change in polarity) then allows the inverted ripple injection signal to be summed against the AC mains supply wave input signal so that the summation results in the cancellation of the ripple injection signal and an even smaller delay of the AC mains supply wave so that the generation of the timing reference signal is ultimately unaffected by the ripple injection signal and available much sooner than possible when low pass filtering is used to decrease the amplitude and therefore effect of the ripple signal.

[037] As the timing signal reference is made available prior to the AC mains supply input wave signal next zero crossing, this generated timing reference signal places no timing restriction on the lamp under the control of the dimmer arrangement turn OFF time thereby allowing a minimum of zero for the lamp ON time.

[038] In a further form of the invention there is provided a dimmer arrangement for minimising the effects of a ripple injection signal upon an AC mains supply input wave signal received by the dimmer arrangement when controlling luminosity to a lamp under the control of the dimmer arrangement, said dimmer arrangement including:

[039] a filter for filtering a ripple injection signal from an AC mains supply input wave signal having said ripple injection signal superimposed thereon said AC mains supply input wave signal;

[040] a means adapted to phase shift the filtered ripple injection signal180° to provide for an inverted filtered ripple injection signal; [041] a means to combine the inverted filtered ripple injection signal with the AC mains supply input wave signal having the ripple injection signal superimposed thereon, wherein the combining of the inverted filtered ripple injection signal with the AC mains supply input wave signal having the ripple injection signal superimposed thereon eliminates the ripple injection signal and generates an AC mains supply wave signal to which a true zero crossing detection signal is derivable therefrom;

[042] wherein the true zero crossing detection signal is generated prior to a subsequent true zero crossing of the AC mains supply input wave signal having the ripple injection signal superimposed thereon; and

[043] a microprocessor wherein an input of the true zero crossing detection signal to the microprocessor generates a timing reference signal to control an OFF and/or ON period for a load control arrangement, wherein said load control arrangement is adapted to turn ON or OFF the AC mains supply input wave signal having the ripple injection signal superimposed thereon to a load under the control of the dimmer arrangement for the ON or OFF period determined by the timing reference signal.

[044] In preference the generated timing reference signal from the micro-processor is inputted into a signal amplifier with a low voltage supply, preferably the low voltage supply range of the signal amplifier is between 3.3V to 10 V.

[045] In preference the output from the signal amplifier controls an OFF and/or ON period for a load control arrangement.

[046] In preference the micro-processor receives the true zero crossing detection signal prior to a subsequent AC mains supply input wave signal true zero crossing whereupon availability of the true zero crossing detection signal prior to the next subsequent true zero crossing of the AC mains supply input wave signal places no restriction on the generatable timing reference signal to achieve load turn OFF immediately after the next true zero crossing of the AC mains supply input wave signal thereby permitting a minimum ON time for the load under the control of the dimmer arrangement. [047] In preference the filtering and inverting of the ripple injection signal from the AC mains supply input wave signal having the ripple injection signal superimposed thereon includes an all pass filter.

[048] In preference the all pass filter includes two low pass filter functional blocks.

[049] In preference the all pass filter includes two low pass filter building blocks wherein each low pass filter building block has a nominal cut off frequency set to equal the ripple injection signal to be removed.

[050] In an alternative form of the invention a high pass filter is used to filter the ripple injection signal from the AC mains supply input wave signal having the ripple injection signal superimposed thereon.

[051] In preference the high pass filter is a third order filter.

[052] In preference the third order high pass filter includes a first capacitor, second capacitor and third capacitor wherein each of the first capacitor, second capacitor and third capacitor have a corresponding first resistor, second resistor or third resistor.

[053] In preference each stage of the third order high pass filter is arranged for a 60 phase shift of the ripple injection signal, so that the overall phase shift for the ripple injection signal is 180°.

[054] In preference a transistor is used to invert the overall 180°phase shifted ripple injection signal.

[055] In preference the load control arrangement for turning ON or OFF the AC mains supply wave input signal to the load includes a control switch with back-to- back Field Effect Transistors (FETs). [056] In preference the FETs are N-channelled enhancement mode MOSFETs, with source terminals connected together with gates connected together and the drain terminals of each back-to-back FET connected to a corresponding active terminal or load terminal.

[057] In preference each FET has an intrinsic body diode so as to allow conduction of current through the two wire trailing edge phase cutting dimmer arrangement in one direction.

[058] The preferred embodiments referenced above provided the cancellation of the ripple injection signal through the unique combining of the inverted filtered ripple injection signal with the AC mains supply input wave signal having the ripple injection signal superimposed thereon, eliminated the ripple injection signal and generated an AC mains supply wave signal from which "a true zero crossing detection signal" is derivable.

[059] The applicant also recognises there is a requirement to achieve a constant phase shifting of the filtered ripple injection single to provide for an inverted ripple injection signal not only at just a single frequency but over a range of frequencies while preserving minimal phase shift of the AC mains supply input wave signal of 50 Hz or 100 Hz after rectification, which in practice is difficult to achieve.

[060] Hence in further form of this invention rather than simply cancelling a single frequency associated with a ripple injection signal, there would be in a practical sense an attenuation of a range of interfering ripple injection frequencies.

[061] Accordingly in a further form of the invention there is provided a method for controlling dimming of a dimmer arrangement to minimise the affects of a ripple injection signal superimposed upon an AC mains supply input wave signal received at the dimmer arrangement voltage terminals, said method including at least the steps of: [062] providing a reduced scaled replicated AC mains supply input wave signal affected by a ripple injection signal from an AC mains supply input wave signal affected by a ripple injection signal;

[063] making available said reduced scale replicated AC mains supply input wave signal affected by the ripple injection signal to a first signal pathway and a second signal pathway;

[064] said first signal pathway including a high-pass filter, wherein the high-pass filter has a cut off frequency above a frequency of the AC mains supply input wave signal affected by the ripple injection signal, such that the high-pass filter passes only ripple injection frequencies of the ripple injection signal above the AC mains supply input wave signal affected by the ripple injection signal;

[065] inverting the ripple injection signal passed by the high-pass filter of the first signal pathway;

[066] combining the inverted ripple injection signal passed by the high-pass filter of the first signal pathway to the reduced scaled replicated AC mains supply input wave signal affected by the ripple injection signal made available on the second signal pathway wherein the combining of the inverted ripple injection signal passed by the high-pass filter with the AC mains supply input wave signal having the ripple injection signal superimposed thereon eliminates the ripple injection signal thereby providing an AC mains supply wave signal from which a true zero crossing detection signal is derivable;

[067] wherein an input of the derived true zero crossing detection signal to a gate drive arrangement of the dimmer arrangement generates a timing reference signal to control an OFF or ON period for a load control arrangement of the dimmer arrangement, wherein said load control arrangement is adapted to turn OFF or ON the AC mains supply input wave signal affected by the ripple injection signal to a lamp under the control of the dimmer arrangement for an ON or OFF period determined by the timing reference signal. [068] In preference inverting of the ripple injection signal passable by the high-pass filter of the first signal pathway includes a differential amplifier.

[069] In preference the ripple injection signal passable by the high-pass filter of the first signal pathway is inputtable into an inverting input of the differential amplifier.

[070] In preference the reduced scale replica of the AC mains supply input wave signal affected by the ripple injection signal made available on the second signal pathway is inputtable into a non-inverting input of the differential amplifier.

[071] In preference the reduced scaled replicated AC mains supply input wave signal affected by the ripple injection signal from the AC mains supply input wave signal affected by the ripple injection signal at the dimmer voltage terminals is provided through an attenuator network.

[072] In preference the attenuator network includes a plurality of resistors in series between the dimmer arrangement voltage terminals.

[073] In preference the series of resistors of the attenuator network includes four resistors in series.

[074] In preference a third signal pathway is provided from the output of the differential amplifier.

[075] In preference the third signal pathway includes a high-pass filter wherein the high-pass filter is configured in parallel with a feedback resistor of the differential amplifier and wherein the third signal pathway is electrically connected to the second signal pathway input into the inverting input of the differential amplifier.

[076] In preference the high-pass filters on the first signal pathway and the third signal pathway are series configured capacitor and resistor arrangements. [077] With the addition of the high-pass filter on the third signal pathway out from the output of the differential amplifier assists in compensating for the phase shift caused by the high-pass filter of the first signal pathway so as to achieve a greater degree of ripple injection frequency cancellation of the ripple injection signal at the output of the differential amplifier.

[078] In preference the output from the differential amplifier provides for an AC mains voltage signal with zero or a substantially attenuated ripple injection signal wherein the AC mains voltage signal with a zero and/or substantially attenuated zero ripple injection signal appears as an input to the inverting input of a comparator wherein a reference voltage is connected to a positive input of said comparator.

[079] In preference the output from said comparator provides for the true zero crossing detection signal which is inputted into a micro-processor that generates a timing reference signal from the micro-processor.

[080] In preference the generated timing reference signal from the micro-processor is inputted into a signal amplifier with a low voltage supply, preferably the low voltage supply range on the signal amplifier is between 3.3 volts to 10 volts.

[081] In preference the outputted signal from the signal amplifier controls the OFF and/or ON period of the dimmer under the control of the dimmer arrangement.

[082] In preference a low-pass filter with a cut off frequency to avoid any significant delay of the output signal from the comparator is included along the signal path from the output from the differential amplifier into the inverting input of the comparator.

[083] In an alternative embodiment of the invention, inversion of the ripple injection frequencies of the ripple injection signal passed by the high-pass filter of the first signal pathway are inverted through a transistor arrangement.

[084] In preference the transistor arrangement includes a pair of transistors, wherein each transistor is of substantially similar characteristics. [085] In preference the pair of transistors are identical.

[086] In preference the two identical transistors making up the transistor

arrangement for inverting the ripple injection frequencies of the ripple injection signal affecting the AC mains supply input wave signal are PNP bipolar junction transistors, wherein the bases of each identical PNP bipolar junction transistors are joined and wherein each of the identical PNP bipolar junction transistors emitter resistors are substantially equal.

[087] In preference said reduced scale replicated AC mains supply input wave signal affected by the ripple injection signal is made available to a third signal pathway.

[088] In preference said third signal pathway configured to be enabled when the amplitude of the reduced scale replicated AC mains supply input wave signal falls below a variable threshold level determined by processing said reduced scale replicated AC mains supply input wave signal, thereby ensuring generation of a timing reference signal when unavailable from the combined first signal pathway and the second signal pathway.

[089] In preference a fourth signal pathway is provided from the output of the differential amplifier.

[090] In preference the fourth signal pathway includes a high-pass filter wherein the high-pass filter is configured in parallel with a feedback resistor of the differential amplifier and wherein the fourth signal pathway is electrically connected to the second signal pathway input into the inverting input of the differential amplifier.

[091] In preference the high-pass filters on the first signal pathway and the fourth signal pathway are series configured capacitor and resistor arrangements.

[092] The addition of the high-pass filter on the fourth signal pathway out from the output of the differential amplifier assists in compensating for the phase shift caused by the high-pass filter of the first signal pathway so as to achieve a greater degree of ripple injection frequency cancellation of the ripple injection signal at the output of the differential amplifier.

[093] In order now to describe the invention in greater detail a series of preferred embodiments will be described with the assistance of the following illustrations and accompanying text.

BRIEF DESCRIPTION OF THE DRAWINGS

[094] Figure 1 illustrates an electrical circuit including a high pass filter arrangement for controlling dimming to a load under the control of the two wire trailing edge phase cutting control dimmer arrangement affected by a ripple injection signal upon the AC mains supply input wave signal in a preferred embodiment of the invention.

[095] Figure 2 illustrates an electrical circuit including an all pass filter arrangement for controlling dimming to a load under the control of the two wire trailing edge phase cutting control dimmer arrangement affected by a ripple injection signal upon the AC mains supply input wave signal in a preferred embodiment of the invention.

[096] Figure 3 illustrates an electrical circuit including a differential amplifier as part of the inversion of the ripple injection frequencies of the ripple injection signal superimposed on the AC mains supply input wave signal to the dimmer arrangement.

[097] Figure 4 is an illustration of the electrical circuit of Figure 3 further including componentry to improve the attenuation and/or cancellation of ripple injection frequencies over a narrow frequency range.

[098] Figure 5 illustrates an electrical circuit including a transistor arrangement for assisting in the inversion of the ripple injection frequencies of the ripple injection signal superimposed on the AC mains supply input wave signal to the dimmer arrangement in a preferred embodiment of the invention. [099] Figure 6 shows the electrical circuit of the arrangement of Figure 5 further including the third signal pathway that ensures a timing reference pulse when the voltage across the Dimmer Arrangement voltage terminals becomes so low that the timing reference signal is no longer made available for the circuit shown in Figure 5.

DETAILED DESCRIPTION OF THE DRAWINGS

[0100] Referring to the drawings now in greater detail wherein Figure 1 provides a circuit arrangement for a two wire trailing edge phase cutting control dimmer arrangement shown generally as (10) adapted to provide a stable timing reference signal to control the supply of AC mains supply (12) to the load (14 ) under the control of the dimmer arrangement.

[0101] The AC mains supply referenced as (12) to place this invention in the context of its application also includes the effects of the ripple injection signal and/or the superimposed supply authority ripple control signals which are riding there upon the AC mains supply (12) which is inputted as an AC mains supply input wave signal to the dimmer arrangement (10) active voltage terminal (16) and load voltage terminal (18).

[0102] Field Effect Transistors (FETs) (20) and (22) comprise the switch control for the load (14). As illustrated FETs (20) and (22) are arranged back-to-back and operate in the N-channel enhancement mode having source terminals (21 ) and (23) connected, the gates (25) and (27) of the FETs (20) and (22) are also connected through electrical path (26) with the drain terminals (29) and (31 ) acting as two power terminals.

[0103] The FETs (20) and (22) each have corresponding diodes (13) and (15) that allow conduction of the current in one direction so the configured back-to-back arrangements of the FETs (20) and (22) allow load current to be controlled in either direction. [0104] The dimmer voltage terminals (16) and (18) are rectified by diodes (13) and (15). The diodes (17) and (19) contained in the Field Effect Transistors (FETs) (20) and (22) comprise the load current switch.

[0105] Detection of the true AC mains zero crossing, to be discussed in greater detail shortly hereafter, using comparator (68) produces an output signal referred to as the true zero crossing detection signal (34). In Figure 1 the outputted true zero crossing signal (34) is inputted into a microprocessor (6).

[0106] The input of the derived true zero crossing detection signal (34) into the microprocessor (6) generates a timing reference signal (7) from the micro-processor (6). The generated timing reference signal (7) from the micro-processor (6) is inputted into a signal amplifier (8) with a low voltage supply, preferably the low voltage supply range of the signal amplifier (8) is between 3.3V to 10 V.

[0107] The outputted signal (1 1 ) from the signal amplifier (8) controls the OFF and/or ON period for the load control arrangement of the FETs (20) and (22).

[0108] The outputted signal (1 1 ) from the signal amplifier (8) is configured to turn the FETs (20) and (22) ON through the gate drive resistors (36, 83).

[0109] While again not essential to the workings of this invention, the circuit (10) shown in Figure 1 also includes a zener diode (40) that is selected together with the amplitude of pulsed signal amplifier voltage so that the effective drive source impedance to control turn ON of the FETs (20) and (22) is resistor (83) while the turn OFF time is determined by the larger impedance of resistor (83) in series with resistor (36) to ground.

[01 10] The main purpose of this invention however is to be able to provide a method and arrangement for appropriately controlling the dimming of the lamp, referenced as the load (14) in Figure 1 , despite the fact that the AC mains supply (12) has been affected by a ripple injection signal. [01 1 1] The reason why the dimmer arrangement can appropriately control the dimming of the lamp is because the generated timing reference signal (34) is not affected by this ripple injection signal riding upon the AC mains supply input wave signal into the dimmer terminals (16) and (18).

[01 12] Circuitry within the arrangement shown in Figure 1 has uniquely introduced the inclusion of a high pass filter to separate the ripple injection signal affecting the AC mains supply input wave signal to which this separated inverted ripple injection signal is then added back to the AC mains supply input wave to cancel out the ripple injection signal.

[01 13] The filter arrangement responsible for separating the ripple injection signal from the AC mains supply input wave signal in the preferred embodiment shown in Figure 1 is a high pass filter of the third order using first capacitor (42), second capacitor (44) and the third capacitor (46) in combination with the first resistor (48), second resistor arrangement of resistors (50, 75) and third resistor (52) wherein the effective value for resistance associated with the second capacitor (44) is the parallel arrangement of the second resistor arrangement including resistors (50) and (75).

[01 14] Each stage of the third order filter, that being the first capacitor (42) with the first resistor (48), the second capacitor (44) with the second resistor arrangement including resistors (50, 75) and the third capacitor (46) with the third resistor (52) are configured to provide a 60° phase shift at the ripple injection signal frequency thereby providing an overall phase shift for the ripple injection signal frequency, that has affected the AC mains supply input wave signal, of 180°.

[01 15] A first transistor (54) inverts the overall phase shifted 180° ripple injection signal so the phase of current referenced by way of arrow (58) will match the ripple injection signal frequency phase at the dimmer terminal voltages (16) and (18) shown after rectification through the rectifier diodes (13) and (15), represented as V_in shown along electrical path line (59). The gains at the first transistor (54) and at the second transistor (62) are adjusted to compensate losses within the third order filter utilising the first capacitor (42), second capacitor (44) and third capacitor (46) along with the associated resistors (48), (50) and (52), and the amplitude of the ripple injection signal frequency referenced by way of arrow (58) flowing into the collector (63) of the second transistor (62) so arranged that it provides for a voltage drop across the series resistor (66) which is equal to the rectified ripple injection frequency input of

Vin.

[01 16] This results in zero ripple injection signal content in the AC mains voltage signal appearing as the negative input signal (67) into the comparator (68) wherein a reference voltage is connected to the positive input (71 ) of the comparator (68) which in the preferred embodiment is 10 V.

[01 17] In order to avoid any distortion of the ripple injection signal voltage referenced at V_in the minimum value of the voltage drop across resistor (66) must equal the voltage peak value of the ripple injection signal voltage at V_in. The first transistor (62) is biased with a DC current at least equal to the peak value of l_R that being the current referenced as (58) as this will provide the DC voltage drop across resistor (66). The DC offset results in an increase in the sensed threshold voltage of the AC mains supply input wave signal at the voltage terminals (16) and (18).

[01 18] The diode (70) included within the third order high pass filter path avoids the overloading of either the first transistor (54) or the second transistor (62) when the FETs (20) and (22) switch the load OFF and the active (16) and load (18) dimmer terminals' voltage rises quickly to hundreds of volts.

[01 19] As shown in Figure 1 there are two resistors (82) and (72) used to generate the scaled replica of the dimmer terminal voltage of active (16) and load (18).

[0120] In completing the circuit description shown in figure 1 , resistors (77) and (78) act as respective emitter resistors of the BJT first transistor (54) and the BJT second transistor (62) and along with resistors (75) and (76) assist in the DC biasing for operational functionality of the first transistor (54) and the second transistor (62). [0121] While resistor (66) and (72) assist in generating the requisite timing reference signal (34) and with additional circuitry (not shown) can provide monitoring of the dimmer terminal voltages at the active (16) and load (18) for over-voltage conditions these resistors (72) and (66) do require significant power to be dissipated when the switched ON time to the load (14) is small.

[0122] Hence it would be advantageous to be able to also reduce power wasted in control components, such as the requirement of two voltage reducing resistors (66) and (72) as is the case with the circuit shown in figure 1 . The circuit illustrated in Figure 2 attempts to do this as well as better meeting the main objectives of this invention.

[0123] Figure 2 shows a further preferred embodiment of the invention wherein rather than using a high pass filter used to separate the ripple injection frequency an "all pass filter" is included within the circuitry.

[0124] The all pass filter does not change the amplitude of the signals of any frequency that passes through the all pass filter. Only the phase of the signals is changed so accordingly the signal is just delayed but not changed in amplitude. If the all pass filter is designed to delay the ripple injection signal frequency by 180° then any ripple injection signal input into the all pass filter will not be changed in amplitude at the all pass filter output, the inputted ripple injection signal will only be inverted. That means the inputted ripple injection signal will have the same amplitude, but opposite polarity to the ripple injection signal going into the all pass filter.

[0125] If the output of the all pass filter is summed with the input to the all pass filter, these two opposite voltages of the outputted inverted (opposite polarity) ripple injection signal with the inputted ripple injection signal to the all pass filter would cancel to produce no signal at the relevant ripple injection signal which is affecting the AC mains supply input wave signal. [0126] One representative example of a kind of all pass filter in a preferred embodiment of this invention is shown in Figure 2 wherein the circuit is shown generally as (90).

[0127] The all pass filter shown in circuit (90) is based on, for the most part, two low pass filter building blocks shown generally as (92) and (94) having a nominal cut-off frequency set to equal the frequency of the ripple injection signal frequency to be removed, for example which could be 750Hz.

[0128] The first low pass filter building block (92) of the all pass filter includes the associated componentry of the op-amp (93), resistors (84), (85) and (86) along with capacitor (87) and the second of the low pass filter building blocks (94) includes the op-amp (98) and associated resistors (99), (100) and (101 ) along with capacitor (102).

[0129] This invention makes no claim over the all pass filter configuration per se, but it is the unique implementation of the all pass filter into the circuit (90) of Figure 2 to deal with the effects of the ripple injection signal upon the AC mains supply input wave signal that is significant for this invention.

[0130] The inclusion of the all pass filter within the circuit (90) shown in Figure 2 allows for, the filtering and inverting of the ripple injection signal so as it can be separated and then combined back with the AC mains supply wave input signal affected by the ripple injection signal so that the ripple injection signal can be cancelled out so that the appropriate timing signal reference can be generated and made available accurately before the next subsequent AC mains supply zero crossing.

[0131] The output voltage amplitude (106) is equal to the input signal voltage (108) for all input frequencies into the all pass filter made up of the functional blocks (92) and (94). The all pass filter phase shift varies with the input frequency but is always double the phase shift of the basic low pass filters (92) and (94) used to build the all pass filter. If the resistors (86) and (101 ) in connection with the respective capacitors (87) and (102) for each of the low pass filter functional blocks (92) and (94) has a cutoff frequency equal to a 750Hz ripple injection frequency, each R/C stage has a 45° phase shift at that ripple injection frequency 750Hz. Accordingly, the filter phase shift is twice the shift of each stage, thereby providing a 180° phase shift at the ripple injection frequency.

[0132] When the all pass filter output (106) is summed with the filter input (108) the resultant voltage at (1 10) between the two summing resistors (1 1 1 ) and (1 12) will be approximately equal to the input signal amplitude and its phase shift/delay will be approximately half the phase shift of the AC mains supply wave input signal that appears at the filter output (106) because that output signal has been added to a signal equal in amplitude and having no phase shift.

[0133] As the amplitude of the ripple injection frequency component is equal at the high pass filter input (108) and at the high pass filter output (106) but the phasing of the ripple injection signal is 180° different, the ripple injection frequency is cancelled so the sum signal then provides a signal (1 10).

[0134] Signal (1 10) is the negative input signal (121 ) into the comparator (120) wherein a reference voltage is connected to a positive reference input (122) of the comparator (120). Using comparator (120) produces an output signal referred to as the true zero crossing detection signal (123). In Figure 2 the outputted true zero crossing signal (123) is inputted into a microprocessor (124).

[0135] The input of the derived true zero crossing detection signal (123) into the micro-processor (124) generates a timing reference signal (125) from the microprocessor (124). The generated timing reference signal (125) from the microprocessor (124) is inputted into a signal amplifier (126) with a low voltage supply, preferably the low voltage supply range of the signal amplifier (126) is between 3.3V to 10 V. [0136] The outputted signal (127) from the signal amplifier (126) controls the OFF and ON period for the load control arrangement of the FETs (20) and (22).

[0137] The outputted signal (127) from the signal amplifier (126) is configured to turn the FETs (20) and (22) ON through the gate drive resistors (36, 128).

[0138] Advantageously in the circuit shown in Figure 2 there is only the requirement to use a single voltage divider referenced as resistor (91 ) in conjunction with resistor (129) to replicate the active (16) and load (18) dimmer terminal voltage thereby minimizing power wasted in control components that one would expect from more traditional low pass filtering techniques which require multiple resistors to be used as the voltage dividers to scale the dimmer terminal voltage to levels that can be handled by low voltage detection components that are required to provide two separate timing signals, one to turn the FETs (20), (22) ON near mains zero cross and a second, in conjunction with a timer, to turn the FETS (20), (22) OFF.

[0139] The phase shift of the 100 Hz signal through the All-pass filter, when set to reject 750 Hz will be about 30 degrees. That is equivalent to a signal delay of 0.84 ms. When summed with the input the resultant signal will have a delay of just 0.42 ms. For 230V/50Hz mains falling at 106 V/ms as it approaches zero crossing that means selecting any sensing level detection threshold of the mains above 44.5 V will give a timing signal that is available before mains zero crossing.

[0140] A practical threshold will be just above 50 V so the timing signal will be produced slightly earlier in time and so allows enough time for a microcontroller to sense it and turn the FETs in the load switch ON at close to true mains zero crossing.

[0141] This invention will make it possible to use a terminal voltage level detector to produce two timing signals.

[0142] The conventional 'zero crossing' indication signal will be produced as the dimmer terminal voltage is crossing a detection level as it is decreasing towards zero volts. Significantly another timing signal will be produced while the dimmer's terminal voltage is rising after the dimmer's FETs switch turns OFF.

[0143] The load current becomes near zero so the dimmer's terminal voltage is rising towards a voltage equal to the difference between the mains voltage and the voltage across the load. It will cross a chosen voltage detection threshold at a time, that can be recorded, after the FETs switch was turned OFF. That time provides information about the lamp load impedance that can be used to ensure stability of the dimmer's control system.

[0144] In particular, as the user increases the lamp brightness by increasing the conduction time of the dimmer's load switch, that delay can provide information about whether the dimmer terminal voltage will safely rise well above the level necessary for correct level sensing, and timing pulse generation, as the mains voltage and the terminal voltage falls again.

[0145] Advantageously it becomes possible for the dimmer's control system to monitor the rise of its terminal voltage and inhibit a user's attempt to select a high brightness level that could result in instability of the dimmer's control system.

[0146] To the circuits detailed it is possible to apply 'clipping' or voltage limiting to the scaled terminal voltage in additional preferred embodiments. That clipping can be arranged so it has no effect on the voltage input to the filter when the dimmer is set to 'brightest' and the voltage is smallest.

[0147] The scaling of the terminal voltage can then be adjusted to produce a larger level input to the filter and detector. The scaled voltage (the input to the filter) can then be limited by a 'clipping' arrangement to prevent it rising above a level of the order of three times its minimum value. When the dimmer is set to the 'dimmest' setting the much larger scaled voltage will be limited by the clipping arrangement for that period of time until the terminal voltage falls below this clipping level. Provided that happens at a point in time that allows the (delayed) filter output to be faithfully producing a filtered version of the filter input at a time before the level detection voltage is reached then that clipping will have no adverse effect on the correct generation of the zero crossing timing pulse.

[0148] Referring to the drawings now in greater detail wherein Figures 3, 4, 5 and 6 provides a circuit arrangement for a two wire trailing edge phase cutting control dimmer arrangement shown generally as (210) in Figure 3, (273) in Figure 4, (274) in Figure 5 and (275) in Figure 6, adapted to provide a stable timing reference signal to control the supply of AC mains supply (212) to the load (214) under the control of the dimmer arrangement.

[0149] The AC mains supply referenced as (212) to place this invention in the context of its application also includes the effects of the ripple injection signal and/or the superimposed supply authority ripple control signals of a range of frequencies which are riding there upon the AC mains supply (212) which is inputted as an AC mains supply input wave signal to the dimmer arrangement active voltage terminal (216) and load voltage terminal (218).

[0150] Field Effect Transistors (FETs) (220) and (222) comprise the switch control for the load (214). As illustrated FETs (220) and (222) are arranged back-to-back and operate in the N-channel enhancement mode having source terminals (221 ) and (223) connected, the gates (225) and (227) of the FETs (220) and (222) are also connected through electrical path (226) with the drain terminals (229) and (223) acting as two power terminals.

[0151] The FETs (220) and (222) each have corresponding diodes (213) and (215) that allow conduction of the current in one direction so the configured back-to-back arrangements of the FETs (220) and (222) allow load current to be controlled in either direction.

[0152] The diodes (217) and (219) contained in the Field Effect Transistors (FETs) (220) and (222) comprise the load current switch. [0153] The circumstances of the provision of the true AC mains zero crossing detection will be discussed in greater detail shortly hereafter, but for a general understanding of the gate drive arrangement to control the switching of FETs (220) and (222) for each of Figures 3, 4, 5 and 6, a zero or a substantially attenuated ripple injection signal of the AC mains voltage signal (a variety derivation thereof to be discussed shortly hereafter) is an input to the inverting input (202) of a comparator (268) wherein a reference voltage (203) is connected to a positive input (204) of the comparator (268) .

[0154] The comparator (268) produces an output signal referred to as the true zero crossing detection signal (234). In Figures 3, 4, 5 and 6 the outputted true zero crossing signal (234) is inputted into a microprocessor (206).

[0155] The input of the derived true zero crossing detection signal (234) into the micro-processor (206) generates a timing reference signal (207) from the microprocessor (206). The generated timing reference signal (207) from the microprocessor (206) is inputted into a signal amplifier (208) with a low voltage supply, preferably the low voltage supply range of the signal amplifier (208) is between 3.3V to 10 V.

[0156] The outputted signal (21 1 ) from the signal amplifier (208) controls the OFF and/or ON period for the load (214) under switch control of the FETs (220) and (222).

[0157] The outputted signal (21 1 ) from the signal amplifier (208) is configured to turn the FETs (220) and (222) ON through the gate drive resistors (236, 283).

[0158] While again not essential to the workings of this invention in Figures 3,4, 5 and 6, the circuits shown in Figure 3, 4, 5 and 6 also includes a zener diode (240) that is selected together with the amplitude of pulsed signal amplifier voltage so that the effective drive source impedance to control turn ON of the FETs (220) and (222) is resistor (283) while the turn OFF time is determined by the larger impedance of resistor (283) in series with resistor (236) to ground. [0159] The main purpose of the embodiments of the invention shown is Figures 3, 4, 5 and 6 is to be able to provide a variety of methods and arrangement for

appropriately controlling the dimming of the lamp, referenced as the load (214) in despite the fact that the AC mains supply (212) has been affected by a ripple injection signal that includes ripple injection frequencies over a range of frequencies

[0160] To minimise the effects of the ripple injection signal made up of ripple injection frequencies over a range of frequencies that have been superimposed upon the AC mains supply input wave signal received at the dimmer voltage terminals (216), (218) of the dimmer arrangement, a reduced scaled replicated of this AC mains supply input wave signal affected by a ripple injection is made available as best seen in Figure 3 to a first signal pathway (302) and a second signal pathway (304).

[0161] The first signal pathway (302) includes a high-pass filter, wherein the high- pass filter includes the series capacitor (306) and resistor (308), and has a cut off frequency above the frequency of the AC mains supply input wave signal, such that the high-pass filter passes only ripple injection frequencies of the ripple injection signal above the AC mains supply input wave signal affected by the ripple injection signal.

[0162] The dimmer terminal voltage between the voltage terminals (216) and (218) has preferably mains voltage levels to nominally 340 V peak and to at least 500 V during AC mains supply transients scaled to a lower voltage to be conveniently processed using low voltage components. The attenuator network to achieve the reduced scaled replicated of this AC mains supply input wave signal affected by the ripple injection over a range of frequencies consists of the resistors (309) nominal value 560k ohms, (310) nominal value 9.1 k ohms, (31 1 ) nominal value 9.1 k ohms and (312) nominal value 9.1 k ohms.

[0163] The 'scaled dimmer terminal voltage' is the voltage appearing at the node referenced as (313) in Figure 3. The voltage value based on the nominal values listed for resistors (309), (310), (31 1 ) and (312) is (9.1 +9.1/9.1 +9.1 +560) times the dimmer terminal voltage of the inputted AC mains supply input wave signal affected by the ripple injection signal. That is approximately .03147 of the terminal voltage providing therefore a nominal peak value for 230V rms mains of about 7.24 V at "S".

[0164] The ripple injection frequencies of the ripple injection signal passable by the high-pass filter including capacitor (306) and resistor (308) of the first signal pathway (302) is inputted into the inverting input (315) of the differential amplifier (316). The differential amplifier (316) also includes a feedback resistor (324).

[0165] Cancellation of the ripple injection frequencies is achieved by combining the inverted ripple injection frequencies of the ripple injection signal passed by the high- pass filter of the first signal pathway (302) into the inverting input (315) of the differential amplifier (316) with the reduced scaled replicated AC mains supply input wave signal affected by the ripple injection signal made available on the second signal pathway (304) which is inputted into the non-inverting input (317) of the differential amplifier (316). Wherein the combining of the inverted ripple injection frequencies of the ripple injection signal passed by the high-pass filter with the AC mains supply input wave signal having the ripple injection signal superimposed thereon eliminates the ripple injection frequencies of the ripple injection signal thereby providing an AC mains supply wave signal with zero content or substantially reduced ripple injection effect, as seen at the output (318) of the differential amplifier (316).

[0166] Accordingly a true zero crossing detection signal is now derivable from the cleaned AC mains supply wave signal with zero content or substantially reduce ripple injection effect found at the output (318) of the differential amplifier (316).

[0167] While the phases of the ripple injection frequencies of ripple injection signal are not exactly matched at the two inputs (315) and (317) of the differential amplifier (316), the amplitudes at the two inputs (315) and (317) are reasonably matched and an attenuation of the ripple frequencies by a factor x3.75 at the output (318) of the differential amplifier (316) is achievable.

[0168] This outcome is similar to the ripple attenuation available at the reference pulse detector in conventional Low-pass filtering arrangements using a cut-off frequency around 130 Hz. The important difference in this invention for the

embodiment shown in Figure 3 is that the delay of the AC mains supply wave input signal frequency component is substantially reduced and it becomes practical to use level detection based on a level that can generate a timing reference pulse before the true zero crossing time of the AC mains supply input wave signal.

[0169] While any form of clipping of the signals in the traditional low-pass filtering arrangement will cause the timing pulse to be displaced by ripple signals, because the total voltage [AC mains supply + ripple injection frequencies] will cease to be clipped at a time that is dependent on that total voltage and so affected by the ripple injection. The variability of that time, after delay by the filter, results in a variable reference time.

[0170] Clipping of the scaled reference voltage in arrangements based on

cancellation will not affect the timing of the zero crossing reference pulse provided the clipping ceases at least 1 ms before the detector threshold level will be crossed. Clipping can therefore be applied as shown by the diode (320).

[0171] Adding resistor (312) with nominal value 9.1 k means that clipping the divided voltage at the junction (321 ) of the resistor (309) nominal value 560k and resistor (310) nominal value 9.1 k is equivalent to clipping the voltage at node (313). The differential amplifier (316) is then only required to handle input signals at low voltage.

[0172] By adding another series capacitor (325) and resistor (326) arrangement as in Figure 4, this also compensates for the phase shift caused by the High Pass filter made up of the series capacitor (306) and resistor (308) arrangement and so achieves an even better degree of ripple injection frequencies cancellation at the output (328) as shown in figure 4. The High pass filter phase and amplitude compensation, when using minimal components to keep it practical, can only be optimised over a narrower range of frequencies but the compensated range is still wide enough to include two of the more important ripple frequencies 750 Hz and 1050 Hz. The arrangement in Figure 4 provides at x8 reduction of 750 Hz and 1050 Hz. [0173] The phasing in the circuit shown in Figure 4 is also compensated by the series capacitor (306) and resistor (308) arrangement and the amplitude as referenced for Figure 3 by adjusting the divider resistor (332) shown in Figure 4 that feeds the non- inverting input (330) of the differential amplifier (331 ). The nominal resistor (312) in Figure 3 valued at 9.1 k has been reduced to 7.5k as resistor (332) in Figure 4.

[0174] There are many alternatives that will produce essentially the same end result. For example the feed back resistor (324) in parallel with capacitor (325) and resistor (326) of Figure 4 or resistor (308) nominally valued as 300k ohms in Figures 3 can be adjusted in value instead of adjusting resistor (332) of Figure 4.

[0175] For the slight increase in complexity the arrangement shown in Figure 4 achieves at least the same ripple rejection frequencies cancellation performance as the traditional Low pass filter but has achieved it with a much smaller delay, allowing the generation of a clean zero crossing timing reference signal before true mains zero crossing. When the phase is compensated around the ripple frequencies the full cancellation of any very high frequency noise that may be present on the AC mains supply is lost.

[0176] Adding a Low Pass filter shown as resistor (336) and capacitor (338) in Figure 4, with a cut-off frequency placed high enough that it does not cause any significant delay of the signal taken at (328), that is to be processed by the level detector comparator (268), provides this arrangement with greater immunity to very high frequency noise. A cut-off frequency above 3 kHz is preferred and in Figure 4 the Low Pass Filter of resistor (336) and capacitor (338) has a -3dB point preferably around 7 kHz.

[0177] The description of operation of this general cancellation arrangement in Figures 3 and 4 has been simplified by reference to an operational amplifier for the realisation of the differential amplifier (316) in Figure 3 and (331 ) in Figure 4 used to achieve the ripple injection frequencies cancellation. It is also possible to achieve the same signal inversion of the ripple injection frequencies required for cancellation using a discrete component arrangement and one preferred embodiment is shown in Figure 5. [0178] In this realisation the signal inversion is achieved using an arrangement in common use inside integrated circuits and called a 'current mirror'. The use of two identical transistors (354) and (356) having bases (358) and (360) joined and equal valued resistors (362), (364) connected in series with transistors (354) and (356) emitters (366), (368) forces the collector currents of the two transistors to be substantially equal. Any current that flows in collector (370) is matched by the current in the other collector (372). For the current levels used in transistors (354) and (356) a typical value for resistors (362), (364) to ensure reasonable matching of collector currents when built with discrete transistors would be about 10k ohms.

[0179] Connecting the collector (370) of one transistor (354) to its base (358) allows a current to be drawn out of that transistor collector (370). As soon as the base voltage rises to the emitter-base voltage required for conduction, about 0.6 V, the current that flows in that transistor collector (370) will equal the total current drawn out of the linked collector-base minus the base current required to support the collector current. If the transistor (354) has a gain typical of small general purpose transistors, for example 200, then the transistor (354) collector (370) current will be just 0.5% smaller than the current drawn out of the linked collector-base junction (371 ).

[0180] When a second transistor (356) has its base (360) connected to transistor (354) base (358) with the second transistor (356) collector (372) returned to some voltage lower than the voltage on transistor (354) collector (370) then it will also draw a base current equal to 0.5% of the current drawn out of transistor (354) collector (370). That means the collector (370) current of transistor (354) is now 1 % smaller than the current drawn out of the joined collector (370) and two bases (358), (360).

[0181] The current sourced by transistor (356) collector (372) will therefore be also 1 % smaller than the current drawn out of transistor (354) collector (370) joined to the two bases (358), (360).

[0182] If the current drawn from transistor (354) Q1 collector-base junction (371 ) is caused by a voltage V1 (not shown) in series with a resistor R1 (not shown) and transistor (356) collector (372) is connected to a resistor equal in value to R1 then the voltage V2 (not shown) developed at the collector (372) of transistor (356) has a magnitude 1 % smaller than the voltage V1 (not shown) and it has the opposite phase or polarity.

[0183] For the purposes of building the ripple injection frequencies cancellation arrangement this inverted voltage can be summed with a non-inverted ripple signal at (384) to cause ripple cancellation.

[0184] The arrangement in Figure 5 contains all the same passive building blocks as in the Op-amp realisation of Figures 3 and 4. However in Figure 5 the inversion is achieved using the current mirror of two identical transistors (354) and (356) having bases (358) and (360) joined and equal valued resistors (362), (364) connected in series with transistors (354) and (356) emitters (366), (368) forces the collector currents of the two transistors to be substantially equal.

[0185] As the ripple injection frequencies signal is AC coupled via capacitor (306) to the current mirror, which resembles a diode (380) connection to the 10 V supply (381 ), it is necessary to provide a discharge path via the diode (380) with polarity opposite to that of the emitter-base of transistor (354).

[0186] The DC bias required for operation of the current mirror of transistors (354) and (356) is derived from the scaled dimmer terminal voltage and no other bias is required.

[0187] Figure 6 shows the arrangement providing the third signal pathway referenced as the broken line arrows "C" that will replace the signal at the ripple cancellation point (384) when the amplitude of the dimmer terminal voltage falls to a level too small to produce the required 1.1V threshold level at the non-inverting input (276) of the comparator (368) inverting signal input (202).

[0188] Figure 6 also shows the First signal pathway as the broken line arrows "A" and the second signal pathway as broken line arrows "B".

[0189] The amplitude of the scaled terminal voltage at (277) is processed by transistors (404) and (406) to determine whether it is sufficient to generate the required 1.1 V threshold required by the comparator (268). [0190] While the AC mains supply switch of the FETs (220) and (222) is ON the gates (225) and (227) of the FETs (220) and (222) will be driven to a voltage typically around +10 V. The gates (225) and (227) voltage of the FETs (220) and (222) is connected via resistor (420) to the base of NPN transistor (418) turning the transistor (418) ON and causing the transistor (418) collector voltage to be held close to zero volts and so discharging capacitor (414) to near zero volts. When FETs (220) and (222) is turned OFF the gates (225) and (227) of the FETs (220) and (222) voltage falls near to zero volts and transistor (418) is turned OFF so draws no collector current and capacitor (414) is free to rise in voltage.

[0191] When the AC mains supply voltage switch is turned OFF the dimmer terminal voltage will rise to a level determined by the time during the mains half cycle at which the switch is turned OFF and the characteristics of the controlled load. It will rise towards a level equal to the AC mains supply voltage at the instant of switch OFF minus any voltage drop across the connected load. For simple resistive loads the terminal voltage approaches the instantaneous AC mains supply voltage because almost no current is drawn by the dimmer arrangement.

[0192] Complex electronic lamp loads typically exhibit a capacitive characteristic because they typically contain a bridge rectifier that feeds a power supply capacitor. Such loads can store a charge so at the instant of load switch OFF the dimmer terminal may exhibit a slow rise towards some voltage less than the instantaneous AC mains supply voltage. Resistive division of that terminal voltage provides the voltage at point "S" with some fraction of the terminal voltage.

[0193] In the arrangement shown it is approximately 1/20 of the dimmer terminals (216) and (218) voltage. The voltage at (277) is connected via resistor (400) to the emitter of NPN transistor (404) whose base is connected via a large valued resistor (422) to a reference voltage shown as 3.3 V (426).

[0194] At the instant of switch OFF transistor (404) will provide a collector current determined by the value of resistor (400) that charges capacitor (414) via diode (416) towards the emitter voltage of transistor (404). [0195] When the dimmer terminal (216) and (218) voltage is small and this

arrangement is operating to provide a replacement signal for the comparator (268) that emitter voltage will be set by the reference voltage to approximately [3.3 V + emitter-base voltage of transistor (404)]. That is approximately 3.9 V. The charging current of capacitor (414) is approximately [(voltage at point (277) - 3.9 V) / value of resistor (400)]. When the voltage at (277) is low, or if the load (214) ON time is long so voltage is only present for a short time, the capacitor (414) will be charged only to a small voltage, for example less than 1 V.

[0196] While the voltage on capacitor (414) remains more than 0.6 V below the voltage at (277) the PNP transistor (406) will be driven ON and can provide drive to the base of NPN transistor (408). If the drive is sufficient to turn ON transistor (408) then its collector will be held near to zero volts and a current will flow in its collector resistor (410). The value of that current is approximately [10 V - 0.6 V / Resistor (410) value].

[0197] That is approximately 9.4 uA. That current will be mirrored by transistor (354)/transistor (356) to provide a similar drive current into resistor (428) causing a voltage drop cross it of [9.4 uA x 200k] = 1.9V so ensuring that the required 1.1V detection level, at least at the instant that the ac switch is turned OFF, will be exceeded.

[0198] This drive should not be applied whenever the level at (277) would have been sufficient to provide the 1.1 V ripple free signal to the comparator (268) as the dimmer terminals (216) and (218) voltage follows the falling Ac mains supply voltage (212) towards its zero crossing.

[0199] During normal operation, with suitable loads and shorter load ON durations, as the voltage at (277) falls during the load (214) OFF time, and the ripple free signal to the comparator (268) falls, this replacement signal path will be inoperative if the terminal voltage has risen during the load OFF time to a large voltage and capacitor (414) has been charged to a large voltage, for example to 3 V. [0200] If capacitor (414) is charged to 3.3 V then transistor (406) can only be conductive if its emitter voltage is greater than 3.9 V. Further, to provide drive to NPN transistor (408) requires the voltage at (277) to be above 4 V. If it is lower transistor (418) will remain OFF.

[0201] When (277) is at 4 V the voltage across resistor (429) will be more than 1 V. Mirror transistor (356) will be delivering the ripple cancellation current into (428), including a dc component caused by the falling voltage across capacitor (306), so when (277) is at 4 V the comparator (268) input (202) will be above the 1 .1V threshold level.

[0202] As the comparator (268) input (202) voltage crosses 1.1 V, to generate the ripple free zero crossing signal, there will be no signal contribution from transistor (408).

[0203] If, after switch OFF, the dimmer terminal voltage does not cause the voltage at (277) to rise above sufficiently above 4 V to cause charging of capacitor (414) then as the dimmer terminals (216) and (218) voltage, and the voltage at (277), is falling towards zero volts transistors (406) and (408) can be conductive for voltages at (277) down to below 1 V. In this case the ripple free signal input to the comparator (268) would have fallen below 1 .1 V but the replacement drive via transistor (408) will remain active to hold the comparator (268) above 1.1 V until the level at (277) falls below 1 V. That is equivalent to a dimmer terminals (216) and (218) voltage below 20 V so a suitable 'zero crossing' signal from the comparator (268) is assured.

Claims

1. A method for controlling dimming of a dimmer arrangement to minimise effects of a ripple injection signal upon an AC mains supply input wave signal received by the dimmer arrangement when controlling luminosity to a lamp under the control of the dimmer arrangement, said method including the steps of: filtering a ripple injection signal from an AC mains supply input wave signal having said ripple injection signal superimposed thereon said AC mains supply input wave signal; phase shifting the filtered ripple injection signal180° to provide for an inverted filtered ripple injection signal; combining the inverted filtered ripple injection signal with the AC mains supply input wave signal having said ripple injection signal superimposed thereon, wherein the combining of the inverted filtered ripple injection signal with the AC mains supply input wave signal having said ripple injection signal superimposed thereon eliminates the ripple injection signal from the AC mains supply input wave signal having said ripple injection signal superimposed thereon providing an AC mains supply wave signal from which a true zero crossing detection signal is derivable; wherein the derived true zero crossing detection signal is generated prior to a subsequent true zero crossing at the dimmer arrangement voltage terminals of the AC mains supply input wave signal having said ripple injection signal superimposed thereon; and wherein an input of the derived true zero crossing detection signal to a gate drive arrangement of the dimmer arrangement generates a timing reference signal to control an OFF or ON period for a load control arrangement of the dimmer arrangement, wherein said load control arrangement is adapted to turn OFF or ON the AC mains supply input wave signal having the ripple injection signal superimposed thereon to a lamp under the control of the dimmer arrangement for an ON or OFF period determined by the timing reference signal.

2. The method of claim 1 wherein the filtering of the ripple injection signal from an AC mains supply input wave signal having said ripple injection signal

superimposed thereon said AC mains supply input wave signal includes a high pass filter.

3. The method of claim 1 wherein the filtering of the ripple injection signal from an AC mains supply input wave signal having said ripple injection signal

superimposed thereon said AC mains supply input wave signal includes an all pass filter.

4. The method of any one of claims 1 to 3 wherein the gate drive arrangement includes a micro-processor wherein the micro-processor is adapted to provide the timing reference signal upon an inputting of the derived true zero crossing detection signal into the micro-processor.

5. The method of claim 4 wherein the generated timing reference signal from the micro-processor is inputted into a signal amplifier.

6. The method of claim 5 wherein the signal amplifier is adapted to provide an output based on the timing reference signal inputted into the signal amplifier to control the OFF or ON period for the load control arrangement.

7. The method of claim 3 wherein the all pass filter includes two low pass filter functional blocks wherein each low pass filter functional blocks has a nominal cut off frequency set to equal the ripple injection signal superimposed thereon the AC mains supply input wave signal.

8. The method of claim 2 wherein the high pass filter is a third order high pass filter and wherein the third order high pass filter includes a first capacitor, second capacitor and third capacitor wherein each of the first capacitor, second capacitor and third capacitor have a corresponding first resistor, second resistor or third resistor.

9. The method of claim 8 wherein each stage of the third order high pass filter is arranged for a 60° phase shift of the ripple injection signal superimposed thereon the AC mains supply input wave signal, so that the overall phase shift for the ripple injection signal is 180°.

10. The method of claim 9 wherein a transistor arrangement is used to invert the 180° phase shifted ripple injection signal.

1 1. A method for controlling dimming of a dimmer arrangement to minimise the affects of a ripple injection signal superimposed upon an AC mains supply input wave signal received at the dimmer arrangement voltage terminals, said method including at least the steps of: providing a reduced scaled replicated AC mains supply input wave signal affected by a ripple injection signal from an AC mains supply input wave signal affected by a ripple injection signal; making available said reduced scale replicated AC mains supply input wave signal affected by the ripple injection signal to a first signal pathway and a second signal pathway; said first signal pathway including a high-pass filter, wherein the high-pass filter has a cut off frequency above a frequency of the AC mains supply input wave signal affected by the ripple injection signal, such that the high-pass filter passes only ripple injection frequencies of the ripple injection signal above the AC mains supply input wave signal affected by the ripple injection signal; inverting the ripple injection signal passed by the high-pass filter of the first signal pathway; combining the inverted ripple injection signal passed by the high-pass filter of the first signal pathway to the reduced scaled replicated AC mains supply input wave signal affected by the ripple injection signal made available on the second signal pathway wherein the combining of the inverted ripple injection signal passed by the high-pass filter with the AC mains supply input wave signal having the ripple injection signal superimposed thereon eliminates the ripple injection signal thereby providing an AC mains supply wave signal from which a true zero crossing detection signal is derivable; wherein an input of the derived true zero crossing detection signal to a gate drive arrangement of the dimmer arrangement generates a timing reference signal to control an OFF or ON period for a load control arrangement of the dimmer

arrangement, wherein said load control arrangement is adapted to turn OFF or ON the AC mains supply input wave signal affected by the ripple injection signal to a lamp under the control of the dimmer arrangement for an ON or OFF period determined by the timing reference signal.

12. The method of claim 1 1 wherein inverting of the ripple injection signal passable by the high-pass filter of the first signal pathway includes a differential amplifier.

13. The method of claim 12 wherein the ripple injection signal passable by the high-pass filter of the first signal pathway is inputtable into an inverting input of the differential amplifier.

14. The method of claim 13 wherein the reduced scale replica of the AC mains supply input wave signal affected by the ripple injection signal made available on the second signal pathway is inputtable into a non-inverting input of the differential amplifier.

15. The method of claim 14 wherein the reduced scaled replicated AC mains supply input wave signal affected by the ripple injection signal from the AC mains supply input wave signal affected by the ripple injection signal at the dimmer voltage terminals is provided through an attenuator network.

16. The method of claim 1 1 wherein said reduced scale replicated AC mains supply input wave signal affected by the ripple injection signal is made available to a third signal pathway.

17. The method of claim 16 wherein said third signal pathway is configured to be enabled when the amplitude of the reduced scale replicated AC mains supply input wave signal falls below a variable threshold level determined by processing said reduced scale replicated AC mains supply input wave signal, thereby providing generation of a timing reference signal when unavailable from the combined first signal pathway and the second signal pathway.

18. The method of claim 17 wherein a fourth signal pathway is provided from the output of the differential amplifier.

19. The method of claim 18 wherein the fourth signal pathway includes a high- pass filter wherein the high-pass filter is configured in parallel with a feedback resistor of the differential amplifier and wherein the fourth signal pathway is electrically connected to the second signal pathway input into the inverting input of the

differential amplifier.

20. The method of claim 19 wherein the high-pass filter on the first signal pathway and the high pass filter on the fourth signal pathway include series configured capacitor and resistor arrangements.