Australian Patents Act 1990 - Regulation 3.2 ORIGINAL COMPLETE SPECIFICATION STANDARD PATENT Invention Title Circuit arrangement for an antenna tuning system using a non-volatile memory and a voltage bootstrapping circuit in passive RFID systems The following statement is a full description of this invention, including the best method of performing it known to me/us: P/00/0 Il 1z A P:\WPDOCS\KMH\Speficaons\Drover Ay One\20197617 specidoc.8/31/20O7 Circuit arrangement for an antenna tuning system using a non-volatile memory and a voltage bootstrapping circuit in passive RFID systems Background of the Invention 5 The present invention relates to a circuit arrangement for an antenna tuning system using a non-volatile memory in RFID systems in conjunction with a voltage- bootstrapping circuit to improve performance of a conventional resonant-frequency tuning system. Description of the Prior Art 10 The reference in this specification to any prior publication (or information derived from it), or to any matter which is known, is not, and should not be taken as, an acknowledgement or admission or any form of suggestion that that prior publication (or information derived from it) or known matter forms part of the common general knowledge in the field of endeavour to which this specification relates. 15 In a passive RFID system employing a RFID microchip with a LC resonant circuit or a "Tank" circuit, the RFID microchip only relies on the energy transmitted or induced from a RFID reader or an interrogator in the form of magnetic field coupling, therefore no energy or external power sources is required. A "RFID tag" or "tag", can be made in various forms depending on the application and consists of a microchip attached to the LC 20 resonator circuit. The RFID microchip communicates with the reader through the tank circuit performing a transponder function. The LC tank loads the reader's magnetic field and energizes the microchip generating a magnetic field feedback to the RFID reader. For example, in a sequential RFID system, the microchip gradually accumulates the field energy until the stored power reaches an adequate level before transmitting its data 25 back to the reader. After an appropriate energizing time, the reader ceases to generate the magnetic field, the microchip then begins sending its data back to the reader in the form of magnetic field conforming to the protocol recognized by the reader. The reader decodes the data from the signal picked up at the reader antenna until the microchip completes the transmission of the telegram. The communication through magnetic field is the key 30 characteristic in the low frequency (100kHz -150kHz) and high frequency RFID applications (13.56Mhz). However, the read distance of a magnetically coupling system is very short especially when designed for small portable readers. Typically, the read distance P :WPDOCS\KMKSpoofcabons\Drovers Ay On\20197617 spec doc-831/2007 -2 achieved ranges from 5 to 20 centimeters. Such distance deems inadequate in many applications. The limited surface area of an antenna and the insufficient energy from the reader are therefore the main limiting factor for most of the small reader systems. Many RFID developers attempt to improve the transponders' efficiency to extend 5 the read distance as much as possible. Due to the fact that read distance is principally dependent on how efficiently the tag can aggregate the energy from the magnetic field transmitted from the reader, hence the key technique by far has been the emphasis on maximizing or increasing the inductor's quality factor (Q) of the resonant circuit. The higher the Q factor being utilized, resulting in a higher selectivity of antenna system 10 matching, the less the energy loss which directly renders the longer read distance. The typical inductor's and capacitor's tolerances used in most tag manufacturing are 3% and 5%, respectively. As a result, the resonant frequencies can deviate from the system's reference frequency proportionally. Although the discrete inductors and capacitors possess large variations, most manufacturers unavoidably use these normal 15 inductors and capacitors to minimize their costs. If high-Q inductors are opted, the risk of having the short read tags within the production batch can be imminent. The main cause to this shortfall is attributed to the differences in the antenna tuning frequencies of reader and the tags. The higher the Q of the transponder's antenna, the more dramatic loss during energy transfer occurred at the transponders. In practice, the tag manufacturers tend to 20 avoid this problem by selecting the inductors' Q of less than 30 to reduce the wide variation in read distances of the transponders within the production batch. Consequently, the read distance achieved drops considerably. If the microchip operates with an inductor with a Q greater than 30, and its resonant frequency is much close to the reader's reference frequency, the read distance is noticeably increased. In contrast, if the resonant frequency 25 is slightly deviated from the reference frequency due to component variations, the efficiency in accumulating energy is reduced and the read distances within the same batch spreads out and drops. This effect is a fundamental drawback of the LC tank antenna system during mass production. High-Q LC tank inevitably needs a precise frequency tuning in order to operate 30 efficiently. The tuning process involves adjusting the inductance or the capacitance of the tank until its resonant frequency matches the generated RF field frequency of the RFID P \WPDOCS\KMH\Speaficabons\Droers Ay C-ne\20197617 spe doc.8/31/2007 -3 reader. The procedure of fine tuning the inductance and the capacitance may be achieved by physically adjusting the inductor's and the capacitor's geometry. Another commonly used method and generally accepted nowadays is to add a proper small capacitor to incrementally adjust the capacitance until the near exact resonant frequency is reached. 5 However, the production approach using these tuning methods is costly, complicated, and time consuming. A more pragmatic method is to integrate a small tuning capacitor array into a microchip and store a tuning configuration (a configuration value that indicates how many capacitors are needed to achieve a matched frequency) within a non-volatile memory. The tuning capacitors can be connected or disconnected using electronic switches 10 controlled by the signals derived from a tuning control circuitry. During the production, manufacturers can use a specially arranged reader which is designed for tags' tuning purpose to tune every single tag. Such calibrating reader determines the tags' proper tuning capacitance by configuring the capacitor array in the microchip to globally cancel out both variations of the capacitance and the inductance used in the tank. The reader then registers 15 the stored tuning configuration for every tag into the tags' own memory. The LC tolerances thus result in individually different tuning configurations. With this embedded tuning process, the transponders need no physical discrete component changes, simplifying the manufacturing process steps. After the tuning process, all of the tags' resonant frequencies and their read distances are well within the target and become closely matched 20 in the same batch. The types of non-volatile memory devices used to keep the tuning configuration must be of a hard-coded ROM, a PROM or an EEPROM. Sparing the ROM type memory, keeping the configuration in a conventional non-volatile memory has a major drawback. The initial valid state of memory will be at an unknown value until a sufficient level of 25 power supply is reached. In other words, if the capacitor array is controlled by this memory, the LC tank will not get initial valid tuning bits during the start-up phase or at a very low power supply level (all node voltages in the circuit are zero at the beginning). This wake-up event occurs every time the tag is brought first time into the RF field or the tag is approaching the reader from a distance. The same applies after the tag has been idled 30 for a while during which the stored energy inside the tag is fully discharged. As a result, the resonant frequency of the tank can never be initially set to match the system's reader P :WPDOCS\KM~iSpeaficatons\Drovers Ay One\20197617 specdoc- 31207 -4 causing the effective read distance to drop. However, by moving the tag closer to the reader so the memory block can function properly, the tag is optimally tuned, resulting in the read distance being restored to its maximum. The overall effect creates uneven reading results, becomes unpredictable, and a substantial reduction of the read distance at first 5 time-read of the tags. To mitigate such problems, the US5396251 and US5491484 patents proposed the use of a RFID tag with a frequency-tuning network latch directly connected to a specially designed non-volatile memory (e.g. EEPROM and OTP - One Time Programming) operating as a switch. Such approach simplifies the tuning circuit and avoids the 10 aforementioned problem or the first-time-read issue becomes less severe when the tank circuit is made of a high-Q factor inductor. The non-volatile memory switch is configured to operate under the power supply derived directly from the LC tank as low as one volt or when the RF field power is very weak. However, an extremely large custom-designed EEPROM memory array is then inevitably required to render sufficiently low series 15 resistance switches. With this special process technology, reading the tag from a distance away from the reader results in an almost optimally tuned condition. The limitations in the commercially available CMOS process technologies for integrated-circuit fabrication worsen the problem even more. These limitations are primarily due to the use of scaled down sub-micron CMOS technology (minimum 20 transistor length shorter than 0.5 micron). Most semiconductor foundries generally offer their customers standard CMOS memory arrays. These standard memory processes, e.g. Flash and EEPROM, simplify the design configuration and are regularly used to store an identification number and other digital data. Unlike the specific-purpose EEPROM appeared in the case of the prior arts/patents above, the generic memory block that the 25 foundry provides are mostly intended to keep the tuning configuration instead of using the memory devices as direct analog switches. Small-geometry CMOS transistors are usually found in today's integrated circuits for digital sub circuits or controller systems where real estate utilization is to be maximized. The small CMOS devices could, however, run the risk of the oxide breaking 30 down to very moderate operating voltages (<5Volts). For example, for safe operation and reliability, a transistor with a channel length of 0.35 micron should operate with a supply P \WPDOCS\KMKSpooficatos\Drovers Ay C'ne\20197617 spec doc-/31I/2007 -5 voltage no more than 4 volts. However, with the RFID LC tank resonator at close proximity to the reader, the induced AC voltage can readily exceed 9 tol0 volts. A RF limiter together with a voltage regulator to limit the internal supply voltage to a safe operating level is one way to prevent these small transistors from breaking down. The 5 voltage regulator shunts the high DC voltage rectified from the LC tank to a suitable supply level of 2-3 volts on which the memory and most dense digital circuits can safely operate. However, the disadvantage is the required extra supply headroom to operate the regulator properly. Such imperative headroom causes the passive RFID transponders implemented in generic CMOS memory processes to require a higher the minimum 10 induced AC level from the tank circuit than that of the memory circuit fabricated using a custom-design large EEPROM mentioned above, i.e., 4 volts as opposed to 1-2 volts. Summary of the Invention The main invention objective of the "Circuit arrangement for an antenna tuning 15 system using a non-volatile memory and a voltage bootstrapping circuit in passive RFID systems" is to eliminate the issues associated with the passive RFIDs' initial first-read right or short read problem in the antenna tuning system. The new voltage bootstrapping technique permits the use of conventional CMOS memory processes to store the tuning configuration without any change or modification of the process technologies while still 20 setting the tank at the right resonant frequency tuning system during the chip's powering up condition. The circuit feed-forwards the supplied power directly induced from the LC tanks to the voltage regulator and the memory block that are required to be operated at the startup. Therefore, a proper tuning frequency can be initiated at very early voltages. The invention circuit arrangement can automatically disengage the supply bootstrapping and 25 subsequently permits the regulator to take control of the internal supply voltage regulation after the voltage on the LC tank is high enough. Furthermore, the invention includes a timing control that guards the memory accessing during bootstrapping action in order to read the right tuning data accurately allowing the tuned LC tank to resonate at precise frequencies. 30 The invention consists of a frequency-tuning network whose capacitor array can be altered by adjusting the switches' topology inside the network, a memory block that keeps P \WPDOCS\KMH\Speficatons\Droers Ay Cne\2197617 sped doc-8/31/2007 -6 the configuration of the switches in a digital word, and a digital controller that reads these data in the pre-defined period. The invention also includes associated latches used to hold the data configuring the switches. Thus, the capacitance array combination is maintained even when the digital controller departs from configuring the tuning word(code?) to 5 perform other functions of the chip. The digital signals from the latches are up level translated by amplitude level converters to reach the same voltage as the AC amplitude on the LC tank to engage or disengage the switches. In addition, the invention incorporates an AC-to-DC rectifier to obtain the chip's entire DC supply from the LC tank. Also included in the circuit arrangement, to prevent 10 the CMOS digital controller, the memory, and other low-volt circuitry which operates at low supply levels (<3 Volts) from being possibly damaged by high-volt supply from the rectifier, a series regulator is employed to convert a large DC voltage from the rectifier (Vfwr) into the internal supply voltage (Vint). The invention principally consists of a bootstrapping switch that connects the 15 voltage Vfwr to Vint, and a voltage-bootstrapping circuit that controls the said switch's state and the tuning-data retrieval. The voltage-bootstrapping circuit monitors the voltage Vfwr and compares its amplitude to a pre-defined reference voltage Vref to determine whether the voltage Vfwr is high enough, implying an adequate operating voltage of the regulator. During the startup, the voltage Vfwr gradually increases, yet it is too low for the 20 regulator to operate. Then, the voltage-bootstrapping circuit turns the bootstrapping switch on (short-circuited) allowing the voltage Vfwr to be fed-forward to internal circuitries. Simultaneously, the digital controller, under the control of the voltage-bootstrapping circuit, reads the tuning data from the memory and passes it to the frequency-tuning network. The voltage-bootstrapping circuit turns the bootstrapping switch off when the 25 Vfwr amplitude reaches the pre-defined level, disabling the feed-forwarding action. The voltage-bootstrapping circuit also releases its control over the digital controller and instructs the latches to hold the tuning data that configure the frequency-tuning network, thus completing the frequency-tuning action. In one broad form, the present invention provides a circuit arrangement, using a 30 voltage-bootstrapping circuit to improve performance of a resonant-frequency tuning system, comprising of a resonant circuit, a frequency-tuning network, a rectifier, a voltage P \WPDOCS\KMHSpedflcaions\Droers Ay OneX20197617 spec doc-831/2007 -7 regulator, a latch and level converter, a digital controller and memory and a voltage bootstrapping control system, consisting of a voltage-bootstrapping circuit and a voltage bootstrapping switch, designed such that during the time when a rectified voltage from the resonant circuit is extremely low , the voltage-bootstrapping circuit turns the voltage 5 bootstrapping switch on, permitting the rectified voltage to be used as the internal circuits's supply instead of obtaining it from the voltage regulator. The digital controller reads out tuning data from the memory and passes them to the latch then level translate the data into signals that control the frequency-tuning network by level converters. After the rectified voltage is high enough and without headroom degradation, the regulator can 10 generate the internal supply voltage and supersedes the feed-forward action whereby the voltage-bootstrapping circuit turns the bootstrapping switch off and the latch will keep the tuning data constant. Preferably, the memory is a non-volatile type and has a general memory structure characterized in that the memory space is partitioned into addresses and the tuning data is 15 kept in a specific address while other addresses are used to store general data. Also preferably, the voltage-bootstrapping circuit contains transistors (35-40) connected into a comparator which has the transistor (35) that senses the reference level generated by the transistors (42,43) while the transistor (38) senses the (Vfwr) to compare with the reference level and that the transistors (36,37) add an offset voltage to the 20 comparator thus raising the reference level which is chosen so that the bootstrapping signal (34) toggles at the appropriate level of the reference voltage (Vfwr) or when the internal power supply (Vint) is high enough, that the voltage bootstrapping circuit further contains a long-channel transistor (41) used to generate a local bias current for the voltage bootstrapping circuit (32) while transistors (54-56) mirror the bias current to a transistor 25 (44) biasing the comparator and a transistor (57) biasing the voltage reference, and that the voltage-bootstrapping circuit also contains an inverter (46) that buffers the output of the comparator at the drain terminal of the transistors (35, 39) for using as the bootstrapping signal (34) and another inverter (47) together with a transistor (45) creates the hysteresis in the comparator to increase noise immunity when the (Vfwr) comes close to the reference 30 level.
P:\WPDOCS\KMH\Speancanons\Drve Ay One\2O197617 spec doc-8/31/2007 -8 Brief Description of the Drawings The present invention will become more fully understood from the following description of preferred but non-limiting embodiments thereof, described in connection with the accompanying drawings wherein: 5 FIG. 1 The resonant-frequency tuning system before the improvement; FIG. 2 A signal diagram explaining signals relating to the resonant circuit; FIG. 3A is a signal diagram showing a relationship between the resonant voltage and the read distance of the system in FIG. 1; FIG. 3B is a signal diagram showing a relationship between the resonant voltage and 10 the frequency of the system in FIG. 1; FIG. 3C is a signal diagram showing a relationship between the resonant voltage and time of the system in FIG. 1; FIG. 4 is a resonant-frequency tuning system with a voltage-bootstrapping circuit; FIG. 5 is a circuit diagram of the voltage-bootstrapping circuit; 15 FIG. 6 is a signal diagram explaining signals relating to the voltage-bootstrapping circuit; FIG. 7A is a signal diagram showing the relationship between the resonant voltage and the read distance of the system in FIG. 4; FIG. 7B is a signal diagram showing the relationship between the resonant voltage 20 and the frequency of the system in FIG. 4; FIG. 7C is a signal diagram showing the relationship between the resonant voltage and time of the system in FIG. 4; Detailed Description of the Preferred Embodiments 25 The circuit diagram in FIG. I explains the conventional configuration of a resonant frequency tuning system for a RFID transponder which can be found in other (prior arts(??Diagrams? or previous patents?). It contains: (i) a resonant circuit or a LC tank to be tuned I which principally acts as a RF energy receiver or an antenna for any passive RFID system (ii) a frequency-tuning network 2 connecting in parallel with the LC tank I 30 provides the ability to tune the overall resonant frequency (iii) a full-wave rectifier 3, a subcircuit parallel with the LC tank I converts the AC pulse signals over the RFI and RF2 P \WPDOCS\MH\SpooncatonsDrver Ay One\20197617 spec do-8/31/2007 -9 pins into a useable DC voltage and a ground reference (0 Volt) for system's internal operation. The obtained DC voltage, dubbed a full-wave rectified voltage Vfwr, tracks the peak amplitude of both pulse signals over the RFI or RF2, as shown in FIG. 2. However, the rectified voltage, Vfwr can rise above 10 volts, when the transponder is placed in close 5 proximity to the reader apparatus or in a very strong RF field condition. This high Vfwr deems unsuitable for directly supplying the system's internal circuitry. Most microchip's internal electronics such as a digital controller and a memory 6 implemented using small geometry CMOS transistors for low power and low supply operation can easily be damaged at such high power supply level. Consequently, the resonant-frequency tuning 10 system also incorporates a voltage regulator 4 to act as a voltage stabilizer of the wide varying Vfwr while keeping a safe and stable operating voltage supply, Vint, between 2 and 3 volts for the entire low-supply CMOS operation. FIG. I The resonant-frequency tuning system before the improvement. To tune the resonant frequency, two symmetrical sets of tuning capacitor arrays 9, 15 11, are properly configured in parallel with the main resonance capacitor 8 thus enabling the capacitive resonant-frequency tuning capability. The parallel connections of both tuning-capacitor arrays 9 and 11 to the LC tank 1 are electrically controlled by corresponding tuning-switch sets 10 and 12. Each tuning capacitor in the sets has its accompanying tuning switch to which it is serially connected. All of the capacitances in 20 each set are arranged in a binary weighted manner conforming to the tuning-control signal 19 of which the latch and level converters output from 5 is also a binary word. The tuning control signal 19 governs the connection inside the frequency-tuning network 2. A variety of capacitances can be produced using a combination of each bit in the tuning-control signal 19 to change the total capacitance or the antenna's overall resonant frequency. Both 25 tuning-switch sets 10, 12 are always treated identically in configurations schematically and layout wise to balance out non-ideality due to parasitic capacitors of tuning switches and tuning capacitors on both RFI and RF2 terminals. FIG. 2 A signal diagram explaining signals relating to the resonant circuit. The rectifier 3 consists of PMOS transistors 13, 14 and diodes 15, 16. Both 30 transistors 13, 14 share the same output terminal, to which the rectified voltage Vfwr is defined while both diodes 15, 16 also share their anodes assigned to be the system's P \WPDOCS\KMH\Speficaons\Drovers Ay Cne\20197617 speci doc-8/31/2007 - 10 ground. During a half RF cycle when the voltage RFI is higher than the voltage RF2, the transistor 13 is turned on (short-circuited) while the transistor 14 is turned off (open circuit), transferring the pulse voltage RFl into the Vfwr. When the difference between the RFI and RF2 voltages is large enough (the RF2 voltage falls below the ground reference 5 by approximately 0.6 volt) diode 16 begins conducting the current while diode 15 is completely off. On the other half RF cycle, the RF2 voltage is higher than the RF I voltage, thus the pulse signal on RF2 supplies the Vfwr instead and the operations of both diodes are also reversed, respectively. The tuning-control signal 19 in Fig. I enables an adjustment of the overall resonant 10 frequency by retrieving its pre-defined value from a tuning-configuration data stored in the memory. Generally, the digital controller 6 convey its retrieved data from the memory to other circuits via an output bus 18. When the digital controller 6 adjusts the resonant frequency, it carries the tuning-configuration data over the output bus 18 to the binary-data latches and the signal-level translators 5 whose output controls the frequency-tuning 15 network 2. To maintain the adjustment data value which then keep the adjusted resonant frequency constant, the digital controller 6 uses the latching signal 17 to instruct the binary-data latches 5 to store the tuning-configuration data. Subsequently, the output bus 18 is free to carry other data read from the memory without affecting the tuning-control signal 19 behind the signal-level converters. For proper interfacing between the low-volt 20 and high-volt circuits, the level converters in 5 (operating under the internal supply voltage Vint), translate all logic-level signals held by binary-data latches to which they are attached, into large-swing signals 19 suitable to control the tuning switch sets 10, 12 that tracks the Vfwr or the RF amplitude. The importance of the frequency-tuning network 2 can be illustrated by observing 25 relationships between the rectified voltage Vfwr and the tag-to-reader distance before applying the resonant-frequency tuning systems, as shown in FIG. 3A. Under the same energizing filed from the reader apparatus and a fixed inductor's Q-factor condition, three tags having different LC tanks' resonant frequencies are characterized for their Vfwr's at several distances. Curves 20, 21, and 22 can be simulated and measured from the actual 30 LC tank circuits. The differences between the three tanks Vfwr's response indicate that the read distance is greatly affected by the shift in the tank's center frequencies. This can be P:\WPDOCS\KMH\Speaficatons\Drovers Ay One\20197617 spe doc-&31/2007 -11 further illustrated by the frequency responses of the Vfwr measured at a fixed distance of 23 as shown in FIG. 3B. Given that the reader transmits the RF power to tags using a carrier frequency fP as displayed by an energy spectrum 58, so an ideal resonant frequency for the tank to obtain the maximum power is at the frequency fi. The first tank (residing in 5 the first tag) resonates at the carrier frequency fP having its frequency response as shown by a curve 26 with the highest induced Vfwr compared to others. The second tank gives the frequency response as depicted by curve 27 and resonates at the frequency fl which deviates slightly from the carrier frequency fM. The last tank holds the most deviated frequency response by resonating at the frequency f2 as shown by curve 28. It can be seen 10 from FIG. 3B that, at the same distance, the larger the frequency shift, the smaller the Vfwr induced at the carrier frequency fM. The effect is even more pronounced when the Q-factor of the tank circuits are large (>100). In most RFID applications, the longest read distance that still provides enough RF energy or voltage to the tag becomes the maximum read distance of that tag. Assuming that the distance 23 is the ideal maximum read distance, i.e. 15 no tags can be read beyond the distance 23, the minimum useful Vfwr level will be a voltage level 25. Without the tuning system, only the first tag can be read at the distance 23 while the other two tags are highly likely to encounter a considerable drop in their read distances. FIG. 3A is a signal diagram showing a relationship between the resonant voltage and 20 the read distance of the system in FIG. 1. FIG. 3B is a signal diagram showing a relationship between the resonant voltage and the frequency of the system in FIG. 1. FIG. 3C is a signal diagram showing a relationship between the resonant voltage and time of the system in FIG. I. 25 FIG. 3C shows the rectified voltage Vfwr plot against the time axis when each tag in the vicinity distance of 23 starts receiving the RF power. The first tank shows the fastest response with the Vfwr settling quickly to the level 25, as shown by the curve 29. The Vfwr on the second tank rises slowly and does not approach the level 25 as of the first tank, instead, it only achieves level 24 without any aids from the frequency-tuning system 30 2. Suppose that the Vfwr at the level 24 is high enough to overcome the supply headroom of the regulator 4, hence the internal supply voltage Vint can be generated for the system's P \WPDOCS\MH\Specficabons\rver Ay One\20197617 speca doc-/31/2007 -12 internal circuitries. With the help from the frequency-tuning system, as the Vfwr comes close to the level 24, the tuning-configuration data from the memory and other signals inside the tag are valid and the frequency tuning occurs. Then the resonant frequency of the second tank shifts from the frequency fl to f) (from untuned to tuned condition) and 5 the second tag obtains more power from the reader. After tuning, the settling point of the Vfwr suddenly increases from the level 24 to 25 as depicted by the curve 30. The Vfwr of the second tag finally reaches the steady level 25. However, for the case of tag3 with the largest deviation in its resonant frequency, the supply headroom of the regulator 4 will cause the frequency-tuning action to fail if the Vfwr is lower than the level 24 and settles at 10 much lower level as shown by a curve 31. The tag, in which the tank resides, is then impossible to be read by the reader at the distance 23. This tag must be placed closer to the reader first in order to be tuned and read, then the read distance increases and any successive reading can be done at the distance 23 provided that the tag's supply voltage is still in a good condition. In practice, the first-time read distance is treated as the 15 performance index of the tag. In other words, the third tag is inferior to the others. The shortfall in the reading-distance can be overcome by using the voltage bootstrapping technique. FIG. 4 is a resonant-frequency tuning system with a voltage-bootstrapping circuit. The circuit arrangement for the new resonant-frequency tuning system now includes 20 a voltage-bootstrapping circuit 32 and a bootstrapping switch 33 to improve the system performance as shown in FIG. 4. The voltage-bootstrapping circuit 32 compares the Vfwr to a pre-defined internal reference voltage Vref. If the Vfwr is lower than the reference Vref, a bootstrapping signal 34 is set to the logic high ("1") which is the same voltage level of the Vfwr. On the other hand, when the Vfwr is higher, the bootstrapping signal 34 is set 25 to the logic low ("0") or the feed-forward action is disengaged. The bootstrapping signal 34 takes charge of the latching signal 17 in controlling the binary-data latches 5, and also lends an additional function of turning on the bootstrapping switch 33 to feed the internal supply voltage V'int. During this feed-forward function, the signal 34 also forces the digital controller 6 to retrieve the tuning-configuration data. When the Vfwr is high enough 30 (higher than the reference voltage Vref), the digital controller 6 is freed from retrieving the tuning-configuration data and able to perform other tasks. Unlike the digital controller 6 in P\WPDOCS\MH\Speaficatons\Drvers Ay One\20197617 speci oc.8/1/2007 - 13 the prior-art system that tries to read the tuning-configuration data and performs other tasks alternately even when the Vfwr is still too low, by performing the tuning separately at a much lower Vfwr level, the tank tuning is achieved with first priority and the digital controller 6 can be dedicated in responding to the reader after the tuning-configuration data 5 is latched and the tag is already tuned. The details of the voltage-bootstrapping circuit 32 are shown in FIG. 5. Transistors 35-40 are connected to perform a comparator function. The comparator determines the difference between the two inputs: the bias voltage Vbias generated from transistors 42, 43 at the gate of transistor 35 and the Vfwr at the gate of transistor 38. Transistors 36, 37 add 10 to the input offset voltage to the comparator resulting in an equivalent circuit that uses an ideal comparator with an increased bias voltage V'bias. This equivalent bias voltage or the so-called "pre-defined reference voltage Vref' must be chosen in such a way that the internal supply voltage V'int does not collapse when the bootstrapping switch 33 is turned off (the bootstrapping signal 34 becomes "0"). To avoid the supply disruption, the 15 regulator 4 must obtain a reasonable V'int level for the internal circuitries before the bootstrapping signal 34 is toggled. FIG. 5 is a circuit diagram of the voltage-bootstrapping circuit. The long-channel transistor 41 consisting of a group of transistors connected serially is used instead of an actual resistor to generate a local bias current for the voltage 20 bootstrapping circuit 32. The transistors 54-56 mirror the bias current to a transistor 44 biasing the comparator and a transistor 57 biasing the bias voltage Vbias. An inverter 46 at the drain terminal of the transistors 35 and 39 buffers the output of the comparator for the actual bootstrapping signal 34. Inverter 47 together with a transistor 45 creates a hysteresis in the comparator to increase the overall noise immunity when the Vfwr gets close to the 25 reference voltage Vref. FIG. 6 is a signal diagram explaining signals relating to the voltage-bootstrapping circuit. FIG. 6 shows the timings of the rectified voltage Vfwr and relevant signals when the tag is brought into the RF field from far away. At the very startup, the Vfwr is so 30 extremely low that no transistors in the system can operate and all digital signals are in unknown state. Assuming that the bias current begins to flow in the voltage-bootstrapping P.\WPDOCS\KMH\Speficalons\Drovers Ay One\20i97617 spectdoc-W/31/2007 - 14 circuit 32 when the Vfwr reaches a voltage level 48. However, the Vfwr at this level can still be insufficient to turn on the stacked transistors 36-38. As a result, the bias current is steered to the left branch of the comparator causing its output voltage to fall down and the bootstrapping signal 34 becomes a "I" in turn, setting the bootstrapping switch 33 on. The 5 feed-forwarding continues until the rectified voltage Vfwr reaches the pre-defined reference level 49, which allows the bias current to be divided equally and flow into both left (35,39) and right (36-38,40) branches of the comparator. Though, transistor 45 does not conduct because the output of the inverter 47 still remains at "0". When the Vfwr passes the reference level 49, a major fraction of the bias current flows into transistors 36 10 38 and 40 causing the comparator output to become "1". Afterwards, the bootstrapping signal 34 reverts to "0" and the inverter 47 turns the transistor 45 on, thus bypassing the transistor 36. This results in lowering the reference voltage Vref by which the comparator inherits as a hysteresis effect. With the hysteresis, the signal 34 will change from "0" to "1" when the Vfwr falls below the voltage level 50 lower than the reference level 49, 15 preventing the signal 34 from chattering. During the feed-forward action, the internal supply voltage V'int will be almost identical in level to the Vfwr immediately after the bootstrapping signal 34 changes from an unknown state to "1" as illustrated in FIG. 6. The internal low-volt supply for the digital and non-volatile memory is hence directly injected by the dc level induced from the LC 20 tanks. In other words, the wake up level of the entire control and memory block 6 and the frequency-tuning system 2 is substantially improved as opposed to the tuning system without the bootstrapping technique. After the Vfwr reaches the reference level 49 implying the field energy is sufficient, the signal 34 falls, causing the bootstrapping switch 33 to open. The V'int consequently receives the voltage-supply only through the regulator 25 4. This causes the internal supply voltage V'int to drop to an optimal operational level. While the bootstrapping signal 34 is still "I", the output bus 18 contains the tuning configuration data, which otherwise contains other information when operating under the control of the digital controller 6. The tuning-configuration data are level-converted to the tuning-control signal 19 kept constant by the latches for controlling the frequency-tuning 30 network 2. Without the invented bootstrapping circuit, the regulator 4 requires imperative headroom to stabilize the memory power supply. This results in a non-volatile memory P WPDOCSKMFtSpeaficationsDroers Ay One\20197617 spe doc-8/31/20O7 -15 section which stores the frequency tuning system to fail to deliver valid tuning data at power supply startup condition. The effect of regulator's headroom can hence be illustrated by comparing the internal supply voltages between the V'int (a dashed line in Figure 6) during the bootstrapping circuit being engaged along with the regulator, and the 5 Vint (solid line) when the regulator works by itself. The rectified voltage Vfwr required by the non-volatile memory system lacking the bootstrapping circuit to operate properly is at the voltage level 24 (also shown in FIG. 3) where the internal supply voltage Vint reaches the reasonably low operable voltage level 48. Reducing the required rectified voltage Vfwr to operate the tuning system helps 10 improve the read distance of the aforementioned tag#3 because its tank can now be tuned to achieve the same read distance as the other tags. FIG. 7A is a signal diagram showing the relationship between the resonant voltage and the read distance of the system in FIG. 4. FIG. 7B is a signal diagram showing the relationship between the resonant voltage 15 and the frequency of the system in FIG. 4. FIG. 7C is a signal diagram showing the relationship between the resonant voltage and time of the system in FIG. 4. FIG. 7A now depicts the rectified voltage Vfwr again before and after applying of the voltage-bootstrapping circuit 32. Notice that before having the assistance bootstrapping 20 circuit, instead of tag#3 to operate properly at level 24, the correct-read level for the Vfwr is then lowered to level 48. The tag can be read furthest at a distance 51 for the first time owing to the frequency-tuning system that requires the Vfwr to be at the voltage level 48. The technique can greatly help the tags having high deviated resonant frequencies to be tuned at almost the same distance. The results have been illustrated again in FIG. 7C. The 25 Vfwr on the last tag when the tunning system working with the aid of bootstrapping circuit is shown with curve 53--a significant difference from the previous curve 31 in FIG. 3C because the LC tank has been tuned. The Vfwr finally reaches the useful voltage level 25 previously considered impossible without the voltage-bootstrapping circuit 32 and the bootstrapping switch 33. Note also that in the time domain and the speed to read, all of the 30 tags Vfwr can also be built up faster in comparison to the tags without incorporating the proposed invented circuit arrangement.
P :\VPDOCS\KMHSpecficatonsm\Drovers Ay One\20197617 spoe doc-/31/2007 - 16 The reference numerals in the following claims do not in any way limit the scope of the respective claims. Whilst the present invention has been herein described with reference to preferred embodiments thereof, it will be understood by persons skilled in the art that numerous 5 variations and modifications may be made thereto. All such variations and modifications should be considered to fall within the scope of the invention as broadly hereinbefore described, and as hereinafter claimed.