AU2003263448A1 - Method of calculating an intra-row permutation pattern for an interleaver - Google Patents

Method of calculating an intra-row permutation pattern for an interleaver

Info

Publication number
AU2003263448A1
AU2003263448A1 AU2003263448A AU2003263448A AU2003263448A1 AU 2003263448 A1 AU2003263448 A1 AU 2003263448A1 AU 2003263448 A AU2003263448 A AU 2003263448A AU 2003263448 A AU2003263448 A AU 2003263448A AU 2003263448 A1 AU2003263448 A1 AU 2003263448A1
Authority
AU
Australia
Prior art keywords
interleaver
intra
calculating
row permutation
permutation pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003263448A
Inventor
Sebastien Charpentier
Yordan Tabakov
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of AU2003263448A1 publication Critical patent/AU2003263448A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/276—Interleaving address generation
    • H03M13/2764—Circuits therefore
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/276—Interleaving address generation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3884—Pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
AU2003263448A 2002-09-25 2003-09-15 Method of calculating an intra-row permutation pattern for an interleaver Abandoned AU2003263448A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP02292352 2002-09-25
EP02292352.8 2002-09-25
PCT/IB2003/004058 WO2004030226A1 (en) 2002-09-25 2003-09-15 Method of calculating an intra-row permutation pattern for an interleaver

Publications (1)

Publication Number Publication Date
AU2003263448A1 true AU2003263448A1 (en) 2004-04-19

Family

ID=32039224

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003263448A Abandoned AU2003263448A1 (en) 2002-09-25 2003-09-15 Method of calculating an intra-row permutation pattern for an interleaver

Country Status (2)

Country Link
AU (1) AU2003263448A1 (en)
WO (1) WO2004030226A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4265345B2 (en) 2003-08-22 2009-05-20 日本電気株式会社 Mobile phone, interleave parameter calculation device, method and program
CN100571088C (en) 2004-07-27 2009-12-16 华为技术有限公司 The interleaving and de-interleaving method that a kind of anti-period position disturbs
US7667628B2 (en) 2008-06-23 2010-02-23 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Interleaver for scrambling and information word
DE102008029623A1 (en) * 2008-06-23 2009-12-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Interleaver e.g. intra-row almost rectangular interleaver, for use in e.g. turbo encoder for scrambling information word, has interleaver stage for reading columns, and for arranging digits of row to one another without gap
RU2448358C1 (en) * 2010-11-26 2012-04-20 Государственное образовательное учреждение высшего профессионального образования "Саратовский государственный университет им. Н.Г. Чернышевского" Involutive permutation generator matrix

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6356636B1 (en) * 1998-07-22 2002-03-12 Motorola, Inc. Circuit and method for fast modular multiplication
US6543013B1 (en) * 1999-04-14 2003-04-01 Nortel Networks Limited Intra-row permutation for turbo code
DE10048872A1 (en) * 2000-10-02 2002-04-25 Infineon Technologies Ag Sectional deinterleaving
US6845482B2 (en) * 2001-02-28 2005-01-18 Qualcomm Incorporated Interleaver for turbo decoder

Also Published As

Publication number Publication date
WO2004030226A1 (en) 2004-04-08

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase