AU2003258853A1 - Logical calculation architecture comprising several configuration modes - Google Patents

Logical calculation architecture comprising several configuration modes

Info

Publication number
AU2003258853A1
AU2003258853A1 AU2003258853A AU2003258853A AU2003258853A1 AU 2003258853 A1 AU2003258853 A1 AU 2003258853A1 AU 2003258853 A AU2003258853 A AU 2003258853A AU 2003258853 A AU2003258853 A AU 2003258853A AU 2003258853 A1 AU2003258853 A1 AU 2003258853A1
Authority
AU
Australia
Prior art keywords
configuration modes
logical calculation
several configuration
calculation architecture
architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003258853A
Other languages
English (en)
Inventor
Gaston Cambon
Jerome Galy
Michel Robert
Gilles Sassatelli
Lionel Torres
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Centre National de la Recherche Scientifique CNRS
Universite Montpellier 2 Sciences et Techniques
Original Assignee
Centre National de la Recherche Scientifique CNRS
Universite Montpellier 2 Sciences et Techniques
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Centre National de la Recherche Scientifique CNRS, Universite Montpellier 2 Sciences et Techniques filed Critical Centre National de la Recherche Scientifique CNRS
Publication of AU2003258853A1 publication Critical patent/AU2003258853A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
AU2003258853A 2002-04-03 2003-04-03 Logical calculation architecture comprising several configuration modes Abandoned AU2003258853A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR02/04161 2002-04-03
FR0204161A FR2838208B1 (fr) 2002-04-03 2002-04-03 Architecture de calcul logique comprenant plusieurs modes de configuration
PCT/FR2003/001050 WO2003083696A1 (fr) 2002-04-03 2003-04-03 Architecture de calcul logique comprenant plusieurs modes de configuration

Publications (1)

Publication Number Publication Date
AU2003258853A1 true AU2003258853A1 (en) 2003-10-13

Family

ID=28052085

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003258853A Abandoned AU2003258853A1 (en) 2002-04-03 2003-04-03 Logical calculation architecture comprising several configuration modes

Country Status (5)

Country Link
EP (1) EP1490787A1 (ja)
JP (1) JP2005521949A (ja)
AU (1) AU2003258853A1 (ja)
FR (1) FR2838208B1 (ja)
WO (1) WO2003083696A1 (ja)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6023742A (en) * 1996-07-18 2000-02-08 University Of Washington Reconfigurable computing architecture for providing pipelined data paths
JP3558114B2 (ja) * 1998-02-16 2004-08-25 富士ゼロックス株式会社 情報処理システム
JP3611714B2 (ja) * 1998-04-08 2005-01-19 株式会社ルネサステクノロジ プロセッサ
JP3587095B2 (ja) * 1999-08-25 2004-11-10 富士ゼロックス株式会社 情報処理装置
US6662302B1 (en) * 1999-09-29 2003-12-09 Conexant Systems, Inc. Method and apparatus of selecting one of a plurality of predetermined configurations using only necessary bus widths based on power consumption analysis for programmable logic device
JP2001202236A (ja) * 2000-01-20 2001-07-27 Fuji Xerox Co Ltd プログラマブル論理回路装置によるデータ処理方法、プログラマブル論理回路装置、情報処理システム、プログラマブル論理回路装置への回路再構成方法
JP2002026721A (ja) * 2000-07-10 2002-01-25 Fuji Xerox Co Ltd 情報処理装置
AU2001289737A1 (en) * 2000-07-24 2002-02-05 Pact Informationstechnolgie Gmbh Integrated circuit

Also Published As

Publication number Publication date
JP2005521949A (ja) 2005-07-21
FR2838208B1 (fr) 2005-03-11
EP1490787A1 (fr) 2004-12-29
FR2838208A1 (fr) 2003-10-10
WO2003083696A1 (fr) 2003-10-09

Similar Documents

Publication Publication Date Title
AU2003263957A1 (en) Contact center architecture
AU2002335152A1 (en) Robot-phone
AU2003229066A1 (en) Interface architecture
AU2003290563A1 (en) Leptin-related peptides
AU2002354472A1 (en) Combine
AU2002367810A1 (en) Bis-transition-metal-chelate-probes
AU2002355026A1 (en) Combine
AU2002952559A0 (en) New use
AU2003202694A1 (en) Torero protein
AU2002318053A1 (en) Suplier
AU2002368348A1 (en) Electrosomatogram
AU2003258853A1 (en) Logical calculation architecture comprising several configuration modes
AU2003278718A1 (en) Stars-a muscle-specification-binding protein
AU2002341221A1 (en) Honey-brandy
AU2002348964A1 (en) Snowbike
AU2002344387A1 (en) Multifunction-pillow
AU2003254865A1 (en) Akt2-BINDING PROTEIN
AU2003235537A1 (en) Amber-climatic complex
AU2002100287A4 (en) Tagz designs
AU2002100739A4 (en) Neuramax
AU2002100498A4 (en) Linline
AU2002100026A4 (en) Disc400
AU2002100160A4 (en) Oxidirator
AU2002100280A4 (en) Proshoe
AU2002100468A4 (en) Flexi-edger

Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase