AU2003230251A1 - High-resolution multi-phase clock generator with an array-structured delay-locking loop - Google Patents
High-resolution multi-phase clock generator with an array-structured delay-locking loopInfo
- Publication number
- AU2003230251A1 AU2003230251A1 AU2003230251A AU2003230251A AU2003230251A1 AU 2003230251 A1 AU2003230251 A1 AU 2003230251A1 AU 2003230251 A AU2003230251 A AU 2003230251A AU 2003230251 A AU2003230251 A AU 2003230251A AU 2003230251 A1 AU2003230251 A1 AU 2003230251A1
- Authority
- AU
- Australia
- Prior art keywords
- array
- clock generator
- phase clock
- locking loop
- resolution multi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0071930A KR100483825B1 (en) | 2002-11-19 | 2002-11-19 | High Resolution Multi-Phase Clock Generator Based On Array Of Delay Locked Loops |
KR10-2002-0071930 | 2002-11-19 | ||
PCT/KR2003/000893 WO2004047293A1 (en) | 2002-11-19 | 2003-05-06 | High-resolution multi-phase clock generator with an array-structured delay-locking loop |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2003230251A1 true AU2003230251A1 (en) | 2004-06-15 |
Family
ID=32322252
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2003230251A Abandoned AU2003230251A1 (en) | 2002-11-19 | 2003-05-06 | High-resolution multi-phase clock generator with an array-structured delay-locking loop |
Country Status (3)
Country | Link |
---|---|
KR (1) | KR100483825B1 (en) |
AU (1) | AU2003230251A1 (en) |
WO (1) | WO2004047293A1 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100641360B1 (en) | 2004-11-08 | 2006-11-01 | 삼성전자주식회사 | Delay locked loop and semiconductor memory device comprising the same |
KR100840697B1 (en) * | 2006-10-30 | 2008-06-24 | 삼성전자주식회사 | Delay-locked loop circuit for generating multi-phase clock signals and method of controlling the same |
KR100809714B1 (en) * | 2007-01-03 | 2008-03-06 | 삼성전자주식회사 | Method for generating multi-phase and apparatus adapted to the same |
KR100825800B1 (en) | 2007-02-12 | 2008-04-29 | 삼성전자주식회사 | Wide range multi-phase delay locked loop circuit including delay matrix |
FR2934935B1 (en) * | 2008-08-08 | 2010-12-24 | Centre Nat Rech Scient | MATRIX OF ELECTRONIC CELLS |
JP2011160369A (en) * | 2010-02-04 | 2011-08-18 | Sony Corp | Electronic circuit, electronic apparatus, and digital signal processing method |
US9912328B1 (en) * | 2016-08-23 | 2018-03-06 | Micron Technology, Inc. | Apparatus and method for instant-on quadra-phase signal generator |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3385167B2 (en) * | 1995-10-20 | 2003-03-10 | 松下電器産業株式会社 | System including phase adjustment circuit and phase adjustment method |
JPH09148923A (en) * | 1995-11-24 | 1997-06-06 | Toshiba Microelectron Corp | Oscillation circuit for phase locked loop circuit |
US6100735A (en) * | 1998-11-19 | 2000-08-08 | Centillium Communications, Inc. | Segmented dual delay-locked loop for precise variable-phase clock generation |
JP3519693B2 (en) * | 2000-04-04 | 2004-04-19 | 松下電器産業株式会社 | Multi-phase clock signal generation circuit |
JP4454810B2 (en) * | 2000-08-04 | 2010-04-21 | Necエレクトロニクス株式会社 | Digital phase control method and digital phase control circuit |
-
2002
- 2002-11-19 KR KR10-2002-0071930A patent/KR100483825B1/en not_active IP Right Cessation
-
2003
- 2003-05-06 WO PCT/KR2003/000893 patent/WO2004047293A1/en not_active Application Discontinuation
- 2003-05-06 AU AU2003230251A patent/AU2003230251A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
KR100483825B1 (en) | 2005-04-20 |
KR20040044219A (en) | 2004-05-28 |
WO2004047293A1 (en) | 2004-06-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK6 | Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase |