AU2003205269A1 - Method and program product for creating and maintaining self-contained design environment - Google Patents

Method and program product for creating and maintaining self-contained design environment

Info

Publication number
AU2003205269A1
AU2003205269A1 AU2003205269A AU2003205269A AU2003205269A1 AU 2003205269 A1 AU2003205269 A1 AU 2003205269A1 AU 2003205269 A AU2003205269 A AU 2003205269A AU 2003205269 A AU2003205269 A AU 2003205269A AU 2003205269 A1 AU2003205269 A1 AU 2003205269A1
Authority
AU
Australia
Prior art keywords
creating
program product
design environment
maintaining self
contained design
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003205269A
Inventor
Jean-Francois Cote
Brian John Pajak
Paul Price
Luc Romain
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Logicvision Canada Inc
Original Assignee
Logicvision Canada Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Logicvision Canada Inc filed Critical Logicvision Canada Inc
Publication of AU2003205269A1 publication Critical patent/AU2003205269A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31704—Design for test; Design verification
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AU2003205269A 2002-01-25 2003-01-23 Method and program product for creating and maintaining self-contained design environment Abandoned AU2003205269A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US35097902P 2002-01-25 2002-01-25
US60/350,979 2002-01-25
PCT/US2003/001831 WO2003065147A2 (en) 2002-01-25 2003-01-23 Method and program product for creating and maintaining self-contained design environment

Publications (1)

Publication Number Publication Date
AU2003205269A1 true AU2003205269A1 (en) 2003-09-02

Family

ID=27662987

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003205269A Abandoned AU2003205269A1 (en) 2002-01-25 2003-01-23 Method and program product for creating and maintaining self-contained design environment

Country Status (2)

Country Link
AU (1) AU2003205269A1 (en)
WO (1) WO2003065147A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100361122C (en) * 2004-11-29 2008-01-09 华为技术有限公司 Automatic designing method for ICT test conversion PCB
KR102004852B1 (en) * 2012-11-15 2019-07-29 삼성전자 주식회사 System for designing semiconductor package using computing system and method for the same, device for fabricating semiconductor package comprising the system, semiconductor package designed by the method
CN107729692B (en) * 2017-11-13 2021-07-20 嘉兴倚韦电子科技有限公司 Automatic physical verification method for semi-custom back-end design of integrated circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0600608B1 (en) * 1992-10-29 1999-12-22 Altera Corporation Design verification method for programmable logic design
US6516456B1 (en) * 1997-01-27 2003-02-04 Unisys Corporation Method and apparatus for selectively viewing nets within a database editor tool
US5923675A (en) * 1997-02-20 1999-07-13 Teradyne, Inc. Semiconductor tester for testing devices with embedded memory
US6063132A (en) * 1998-06-26 2000-05-16 International Business Machines Corporation Method for verifying design rule checking software
US6816997B2 (en) * 2001-03-20 2004-11-09 Cheehoe Teh System and method for performing design rule check

Also Published As

Publication number Publication date
WO2003065147A2 (en) 2003-08-07
WO2003065147A3 (en) 2004-01-22

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase