AU2002305261A1 - Fibre channel transceiver - Google Patents

Fibre channel transceiver

Info

Publication number
AU2002305261A1
AU2002305261A1 AU2002305261A AU2002305261A AU2002305261A1 AU 2002305261 A1 AU2002305261 A1 AU 2002305261A1 AU 2002305261 A AU2002305261 A AU 2002305261A AU 2002305261 A AU2002305261 A AU 2002305261A AU 2002305261 A1 AU2002305261 A1 AU 2002305261A1
Authority
AU
Australia
Prior art keywords
fibre channel
channel transceiver
transceiver
fibre
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002305261A
Other languages
English (en)
Inventor
James C. Braatz
Tuan A. Dao
Rodney A. Hughes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Boeing Co
Original Assignee
Boeing Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Boeing Co filed Critical Boeing Co
Publication of AU2002305261A1 publication Critical patent/AU2002305261A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
AU2002305261A 2001-04-27 2002-04-25 Fibre channel transceiver Abandoned AU2002305261A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US28691801P 2001-04-27 2001-04-27
US60/286,918 2001-04-27
US95305701A 2001-09-14 2001-09-14
US09/953,057 2001-09-14
PCT/US2002/013414 WO2002089405A2 (fr) 2001-04-27 2002-04-25 Emetteur-recepteur a canal de fibres optiques

Publications (1)

Publication Number Publication Date
AU2002305261A1 true AU2002305261A1 (en) 2002-11-11

Family

ID=26964139

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002305261A Abandoned AU2002305261A1 (en) 2001-04-27 2002-04-25 Fibre channel transceiver

Country Status (2)

Country Link
AU (1) AU2002305261A1 (fr)
WO (1) WO2002089405A2 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7545899B2 (en) 2004-01-30 2009-06-09 Broadcom Corporation System and method of phase-locking a transmit clock signal phase with a receive clock signal phase
US7593457B2 (en) 2004-01-30 2009-09-22 Broadcom Corporation Transceiver system and method having a transmit clock signal phase that is phase-locked with a receive clock signal phase
US7860096B2 (en) 2004-06-08 2010-12-28 Oracle America, Inc. Switching method and apparatus for use in a communications network
US7733855B1 (en) 2004-06-08 2010-06-08 Oracle America, Inc. Community separation enforcement
US7210056B2 (en) 2004-06-08 2007-04-24 Sun Microsystems, Inc. Low latency comma detection and clock alignment
US7639616B1 (en) 2004-06-08 2009-12-29 Sun Microsystems, Inc. Adaptive cut-through algorithm
US8964547B1 (en) 2004-06-08 2015-02-24 Oracle America, Inc. Credit announcement

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6041821A (ja) * 1983-08-18 1985-03-05 Nec Corp 送信出力電力制御装置
JP3481051B2 (ja) * 1996-06-19 2003-12-22 富士通株式会社 チャージポンプ回路、および、該チャージポンプ回路を有するｐｌｌ回路並びに半導体集積回路
US5950115A (en) * 1997-08-29 1999-09-07 Adaptec, Inc. GHz transceiver phase lock loop having autofrequency lock correction

Also Published As

Publication number Publication date
WO2002089405A2 (fr) 2002-11-07
WO2002089405A3 (fr) 2003-05-22

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase