AU2002255778A1 - Low power operation mechanism and method - Google Patents

Low power operation mechanism and method

Info

Publication number
AU2002255778A1
AU2002255778A1 AU2002255778A AU2002255778A AU2002255778A1 AU 2002255778 A1 AU2002255778 A1 AU 2002255778A1 AU 2002255778 A AU2002255778 A AU 2002255778A AU 2002255778 A AU2002255778 A AU 2002255778A AU 2002255778 A1 AU2002255778 A1 AU 2002255778A1
Authority
AU
Australia
Prior art keywords
low power
operation mechanism
power operation
low
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002255778A
Inventor
Micah Barany
Robert Jackson
Krishnan Ravichandran
Kevin Zhang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2002255778A1 publication Critical patent/AU2002255778A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008Arrangements for reducing power consumption
    • H03K19/0016Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107Substrate region of field-effect devices
    • H01L29/1075Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
AU2002255778A 2001-06-28 2002-03-14 Low power operation mechanism and method Abandoned AU2002255778A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/892,632 2001-06-28
US09/892,632 US6483375B1 (en) 2001-06-28 2001-06-28 Low power operation mechanism and method
PCT/US2002/008088 WO2003003582A2 (en) 2001-06-28 2002-03-14 Low power operation mechanism and method

Publications (1)

Publication Number Publication Date
AU2002255778A1 true AU2002255778A1 (en) 2003-03-03

Family

ID=25400269

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002255778A Abandoned AU2002255778A1 (en) 2001-06-28 2002-03-14 Low power operation mechanism and method

Country Status (6)

Country Link
US (2) US6483375B1 (en)
EP (1) EP1410508A2 (en)
CN (1) CN100355206C (en)
AU (1) AU2002255778A1 (en)
TW (1) TW564540B (en)
WO (1) WO2003003582A2 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6720821B2 (en) 2002-02-21 2004-04-13 Broadcom Corporation Methods and systems for generating interim voltage supplies
JP2003318351A (en) * 2002-04-26 2003-11-07 Sony Corp Semiconductor device
US7348827B2 (en) * 2004-05-19 2008-03-25 Altera Corporation Apparatus and methods for adjusting performance of programmable logic devices
US7129745B2 (en) * 2004-05-19 2006-10-31 Altera Corporation Apparatus and methods for adjusting performance of integrated circuits
US7079426B2 (en) * 2004-09-27 2006-07-18 Intel Corporation Dynamic multi-Vcc scheme for SRAM cell stability control
US20060119382A1 (en) * 2004-12-07 2006-06-08 Shumarayev Sergey Y Apparatus and methods for adjusting performance characteristics of programmable logic devices
US20070153610A1 (en) * 2005-12-29 2007-07-05 Intel Corporation Dynamic body bias with bias boost
US7355437B2 (en) 2006-03-06 2008-04-08 Altera Corporation Latch-up prevention circuitry for integrated circuits with transistor body biasing
US7495471B2 (en) 2006-03-06 2009-02-24 Altera Corporation Adjustable transistor body bias circuitry
US7330049B2 (en) * 2006-03-06 2008-02-12 Altera Corporation Adjustable transistor body bias generation circuitry with latch-up prevention
US7821330B2 (en) * 2008-03-11 2010-10-26 International Business Machines Corporation Method and apparatus for extending the lifetime of a semiconductor chip
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5461338A (en) * 1992-04-17 1995-10-24 Nec Corporation Semiconductor integrated circuit incorporated with substrate bias control circuit
KR0169157B1 (en) * 1993-11-29 1999-02-01 기다오까 다까시 Semiconductor circuit and mos-dram
JP3085073B2 (en) * 1994-01-24 2000-09-04 富士通株式会社 Static RAM
JPH09293789A (en) * 1996-04-24 1997-11-11 Mitsubishi Electric Corp Semiconductor integrated circuit
KR100223770B1 (en) * 1996-06-29 1999-10-15 김영환 Semiconductor memory device
JPH10229165A (en) * 1997-02-17 1998-08-25 Ricoh Co Ltd Semiconductor integrated circuit device
JP3814385B2 (en) * 1997-10-14 2006-08-30 株式会社ルネサステクノロジ Semiconductor integrated circuit device
US6191615B1 (en) * 1998-03-30 2001-02-20 Nec Corporation Logic circuit having reduced power consumption
JPH11355123A (en) * 1998-06-11 1999-12-24 Mitsubishi Electric Corp Buffer using dynamic threshold value mos transistor
TW453032B (en) * 1998-09-09 2001-09-01 Hitachi Ltd Semiconductor integrated circuit apparatus

Also Published As

Publication number Publication date
CN1545761A (en) 2004-11-10
US20030038668A1 (en) 2003-02-27
US6650171B2 (en) 2003-11-18
TW564540B (en) 2003-12-01
EP1410508A2 (en) 2004-04-21
WO2003003582B1 (en) 2004-07-01
WO2003003582A2 (en) 2003-01-09
CN100355206C (en) 2007-12-12
WO2003003582A3 (en) 2004-02-12
US6483375B1 (en) 2002-11-19

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase