AU2002251667A1 - Encapsulation of an integrated circuit - Google Patents

Encapsulation of an integrated circuit

Info

Publication number
AU2002251667A1
AU2002251667A1 AU2002251667A AU2002251667A AU2002251667A1 AU 2002251667 A1 AU2002251667 A1 AU 2002251667A1 AU 2002251667 A AU2002251667 A AU 2002251667A AU 2002251667 A AU2002251667 A AU 2002251667A AU 2002251667 A1 AU2002251667 A1 AU 2002251667A1
Authority
AU
Australia
Prior art keywords
encapsulation
integrated circuit
integrated
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002251667A
Inventor
Richard Mangapul Sinaga
Najib Khan Surattee
Mohamad Yazid
Kok Cheong Bernard Yeong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of AU2002251667A1 publication Critical patent/AU2002251667A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
AU2002251667A 2002-04-04 2002-04-04 Encapsulation of an integrated circuit Abandoned AU2002251667A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SG2002/000053 WO2003094221A1 (en) 2002-04-04 2002-04-04 Encapsulation of an integrated circuit

Publications (1)

Publication Number Publication Date
AU2002251667A1 true AU2002251667A1 (en) 2003-11-17

Family

ID=29398798

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002251667A Abandoned AU2002251667A1 (en) 2002-04-04 2002-04-04 Encapsulation of an integrated circuit

Country Status (2)

Country Link
AU (1) AU2002251667A1 (en)
WO (1) WO2003094221A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5814928B2 (en) * 2010-11-04 2015-11-17 アルプス電気株式会社 Electronic component module

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2723195B2 (en) * 1990-12-14 1998-03-09 松下電工株式会社 Semiconductor package
JPH0730049A (en) * 1993-07-07 1995-01-31 Toshiba Corp Lead frame
JP3519223B2 (en) * 1996-11-26 2004-04-12 富士電機デバイステクノロジー株式会社 Resin-sealed semiconductor device
JP3359521B2 (en) * 1996-12-26 2002-12-24 京セラ株式会社 Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
WO2003094221A1 (en) 2003-11-13

Similar Documents

Publication Publication Date Title
AU2003299608A1 (en) Integrated circuit assembly
AU2002340506A1 (en) Integrated circuit package including miniature antenna
AU2003253227A1 (en) Electronics circuit manufacture
AU2003224606A1 (en) Method of manufacturing an encapsulated integrated circuit package
AU2003278855A1 (en) Improved integrated circuit package and method of manufacturing the integrated circuit package
AU2003288446A1 (en) Power integrated circuits
AU2003284360A1 (en) Integrated circuit having multiple modes of operation
AU2003221927A1 (en) Authentication of integrated circuits
AU2003300399A1 (en) Well regions of semiconductor devices
AU2003290809A1 (en) Flip-flop circuit
AU2003282838A1 (en) Integrated circuit package configuration incorporating shielded circuit element
AU2002247383A1 (en) In-street integrated circuit wafer via
AU2003272895A1 (en) Booster circuit
AU2003301702A1 (en) Electronic components
AU2003291199A1 (en) Package having exposed integrated circuit device
AU2003300400A1 (en) Manufacture and operation of integrated circuit
AU2003207892A1 (en) An interconnect-aware methodology for integrated circuit design
AU2003293540A1 (en) Integrated circuit modification using well implants
EP1477990A4 (en) Semiconductor integrated circuit
AU2003232716A1 (en) An integrated circuit package
EP1489747A4 (en) Semiconductor integrated circuit
AU2003253414A1 (en) An oscillator and an integrated circuit
AU2003282646A1 (en) Isolation circuit
AU2003283959A1 (en) Integrated circuit oscillator
GB0204708D0 (en) Integrated circuit

Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase