AU2002241505A1 - Methods and devices for caching method frame segments in a low-power stack-based processor - Google Patents

Methods and devices for caching method frame segments in a low-power stack-based processor

Info

Publication number
AU2002241505A1
AU2002241505A1 AU2002241505A AU2002241505A AU2002241505A1 AU 2002241505 A1 AU2002241505 A1 AU 2002241505A1 AU 2002241505 A AU2002241505 A AU 2002241505A AU 2002241505 A AU2002241505 A AU 2002241505A AU 2002241505 A1 AU2002241505 A1 AU 2002241505A1
Authority
AU
Australia
Prior art keywords
methods
devices
low
based processor
frame segments
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002241505A
Inventor
Thomas Bottomley
Guillaume Comeau
Michael Majid
Zohair Sahraoui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ZUCOTTO WIRELESS Inc
Original Assignee
ZUCOTTO WIRELESS Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ZUCOTTO WIRELESS Inc filed Critical ZUCOTTO WIRELESS Inc
Priority claimed from PCT/US2001/044031 external-priority patent/WO2002071211A2/en
Priority claimed from PCT/US2001/044035 external-priority patent/WO2002042911A2/en
Priority claimed from PCT/US2001/043957 external-priority patent/WO2002048864A2/en
Priority claimed from PCT/US2001/043444 external-priority patent/WO2002042898A2/en
Priority claimed from PCT/US2001/043829 external-priority patent/WO2002045385A2/en
Publication of AU2002241505A1 publication Critical patent/AU2002241505A1/en
Abandoned legal-status Critical Current

Links

AU2002241505A 2000-11-20 2001-11-20 Methods and devices for caching method frame segments in a low-power stack-based processor Abandoned AU2002241505A1 (en)

Applications Claiming Priority (18)

Application Number Priority Date Filing Date Title
USNOTGIVEN 1991-06-14
US25217000P 2000-11-20 2000-11-20
US60/252,170 2000-11-20
US25655000P 2000-12-18 2000-12-18
US60/256,550 2000-12-18
US27069601P 2001-02-22 2001-02-22
US60/270,696 2001-02-22
US27637501P 2001-03-16 2001-03-16
US60/276,375 2001-03-16
US29052001P 2001-05-11 2001-05-11
US60/290,520 2001-05-11
US32302201P 2001-09-14 2001-09-14
US60/323,022 2001-09-14
PCT/US2001/044031 WO2002071211A2 (en) 2000-11-20 2001-11-20 Data processor having multiple operating modes
PCT/US2001/044035 WO2002042911A2 (en) 2000-11-20 2001-11-20 Stack chunking
PCT/US2001/043957 WO2002048864A2 (en) 2000-11-20 2001-11-20 System registers for an object-oriented processor
PCT/US2001/043444 WO2002042898A2 (en) 2000-11-20 2001-11-20 Interpretation loop for object oriented processor
PCT/US2001/043829 WO2002045385A2 (en) 2000-11-20 2001-11-20 Methods and devices for caching method frame segments in a low-power stack-based processor

Publications (1)

Publication Number Publication Date
AU2002241505A1 true AU2002241505A1 (en) 2002-06-11

Family

ID=41210692

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002241505A Abandoned AU2002241505A1 (en) 2000-11-20 2001-11-20 Methods and devices for caching method frame segments in a low-power stack-based processor

Country Status (1)

Country Link
AU (1) AU2002241505A1 (en)

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase