AU2002234033A1 - Apparatus and method for generating fifo fullness indicator signals - Google Patents

Apparatus and method for generating fifo fullness indicator signals

Info

Publication number
AU2002234033A1
AU2002234033A1 AU2002234033A AU3403302A AU2002234033A1 AU 2002234033 A1 AU2002234033 A1 AU 2002234033A1 AU 2002234033 A AU2002234033 A AU 2002234033A AU 3403302 A AU3403302 A AU 3403302A AU 2002234033 A1 AU2002234033 A1 AU 2002234033A1
Authority
AU
Australia
Prior art keywords
indicator signals
fullness indicator
fifo fullness
generating
generating fifo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002234033A
Inventor
Josephus C. Ebergen
Ian W. Jones
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of AU2002234033A1 publication Critical patent/AU2002234033A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/12—Indexing scheme relating to groups G06F5/12 - G06F5/14
    • G06F2205/126—Monitoring of intermediate fill level, i.e. with additional means for monitoring the fill level, e.g. half full flag, almost empty flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Measuring Volume Flow (AREA)
AU2002234033A 2000-12-19 2001-12-17 Apparatus and method for generating fifo fullness indicator signals Abandoned AU2002234033A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/742,162 US6772243B2 (en) 2000-12-19 2000-12-19 Apparatus and method for generating a partial fullness indicator signal in a FIFO
US09/742,162 2000-12-19
PCT/US2001/048640 WO2002050656A2 (en) 2000-12-19 2001-12-17 Apparatus and method for generating fifo fullness indicator signals

Publications (1)

Publication Number Publication Date
AU2002234033A1 true AU2002234033A1 (en) 2002-07-01

Family

ID=24983724

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002234033A Abandoned AU2002234033A1 (en) 2000-12-19 2001-12-17 Apparatus and method for generating fifo fullness indicator signals

Country Status (3)

Country Link
US (1) US6772243B2 (en)
AU (1) AU2002234033A1 (en)
WO (1) WO2002050656A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4060097B2 (en) * 2002-03-07 2008-03-12 シャープ株式会社 Self-synchronous FIFO memory device and asynchronous information processing device
DE60304470T2 (en) * 2002-06-14 2007-03-15 Koninklijke Philips Electronics N.V. FIFO REGISTER
US20040158626A1 (en) * 2003-02-11 2004-08-12 Douglas Christopher Paul Method and apparatus for monitoring data flow to a router
US8001297B2 (en) * 2005-04-25 2011-08-16 Microsoft Corporation Dynamic adjusting send rate of buffered data
US7886096B2 (en) * 2008-08-08 2011-02-08 Texas Instruments Incorporated Throughput measurement of a total number of data bits communicated during a communication period

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2627903B2 (en) * 1987-09-18 1997-07-09 日本テキサス・インスツルメンツ株式会社 Semiconductor storage device
JPH06119772A (en) * 1991-10-15 1994-04-28 Nec Ic Microcomput Syst Ltd Data fifo storage circuit
US5390299A (en) * 1991-12-27 1995-02-14 Digital Equipment Corporation System for using three different methods to report buffer memory occupancy information regarding fullness-related and/or packet discard-related information
JPH05266202A (en) * 1992-03-24 1993-10-15 Fujitsu Ltd Method and circuit for graphic data transfer in picture plotting processing
US5457688A (en) * 1993-05-07 1995-10-10 The United States Of America As Represented By The Secretary Of The Navy Signal processor having multiple paralleled data acquisition channels and an arbitration unit for extracting formatted data therefrom for transmission
US5513224A (en) * 1993-09-16 1996-04-30 Codex, Corp. Fill level indicator for self-timed fifo
US5838933A (en) 1993-10-21 1998-11-17 Sun Microsystems, Inc. Control circuit and method for a first-in first-out data pipeline
US6055588A (en) * 1994-11-28 2000-04-25 Hewlett-Packard Company Single stage FIFO memory with a circuit enabling memory to be read from and written to during a single cycle from a single clock
US6279077B1 (en) * 1996-03-22 2001-08-21 Texas Instruments Incorporated Bus interface buffer control in a microprocessor
JP3013033B2 (en) * 1997-02-13 2000-02-28 日本電気エンジニアリング株式会社 Storage data amount monitoring circuit
US5920899A (en) 1997-09-02 1999-07-06 Acorn Networks, Inc. Asynchronous pipeline whose stages generate output request before latching data
US6097655A (en) * 1998-04-03 2000-08-01 International Business Machines Corporation Pull through FIFO memory device
US6115760A (en) 1998-08-24 2000-09-05 3Com Corporation Intelligent scaleable FIFO buffer circuit for interfacing between digital domains
US6434642B1 (en) * 1999-10-07 2002-08-13 Xilinx, Inc. FIFO memory system and method with improved determination of full and empty conditions and amount of data stored
US6356117B1 (en) * 2000-09-29 2002-03-12 Sun Microsystems, Inc. Asynchronously controlling data transfers within a circuit

Also Published As

Publication number Publication date
US6772243B2 (en) 2004-08-03
US20020116556A1 (en) 2002-08-22
WO2002050656A3 (en) 2003-08-14
WO2002050656A2 (en) 2002-06-27

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