AU2001279208A1 - Methods and apparatus for enhancing digital signal processors - Google Patents
Methods and apparatus for enhancing digital signal processorsInfo
- Publication number
- AU2001279208A1 AU2001279208A1 AU2001279208A AU7920801A AU2001279208A1 AU 2001279208 A1 AU2001279208 A1 AU 2001279208A1 AU 2001279208 A AU2001279208 A AU 2001279208A AU 7920801 A AU7920801 A AU 7920801A AU 2001279208 A1 AU2001279208 A1 AU 2001279208A1
- Authority
- AU
- Australia
- Prior art keywords
- methods
- digital signal
- signal processors
- enhancing digital
- enhancing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/633,831 US6754805B1 (en) | 2000-08-07 | 2000-08-07 | Method and apparatus for configurable multi-cell digital signal processing employing global parallel configuration |
US09633831 | 2000-08-07 | ||
PCT/US2001/024667 WO2002012978A2 (en) | 2000-08-07 | 2001-08-06 | Configurable function processing cell linear array in computation engine coupled to host units |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2001279208A1 true AU2001279208A1 (en) | 2002-02-18 |
Family
ID=24541293
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2001279208A Abandoned AU2001279208A1 (en) | 2000-08-07 | 2001-08-06 | Methods and apparatus for enhancing digital signal processors |
Country Status (3)
Country | Link |
---|---|
US (1) | US6754805B1 (en) |
AU (1) | AU2001279208A1 (en) |
WO (1) | WO2002012978A2 (en) |
Families Citing this family (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7266725B2 (en) | 2001-09-03 | 2007-09-04 | Pact Xpp Technologies Ag | Method for debugging reconfigurable architectures |
DE19651075A1 (en) | 1996-12-09 | 1998-06-10 | Pact Inf Tech Gmbh | Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like |
DE19654595A1 (en) | 1996-12-20 | 1998-07-02 | Pact Inf Tech Gmbh | I0 and memory bus system for DFPs as well as building blocks with two- or multi-dimensional programmable cell structures |
EP1329816B1 (en) | 1996-12-27 | 2011-06-22 | Richter, Thomas | Method for automatic dynamic unloading of data flow processors (dfp) as well as modules with bidimensional or multidimensional programmable cell structures (fpgas, dpgas or the like) |
US6542998B1 (en) | 1997-02-08 | 2003-04-01 | Pact Gmbh | Method of self-synchronization of configurable elements of a programmable module |
US8686549B2 (en) | 2001-09-03 | 2014-04-01 | Martin Vorbach | Reconfigurable elements |
DE19861088A1 (en) | 1997-12-22 | 2000-02-10 | Pact Inf Tech Gmbh | Repairing integrated circuits by replacing subassemblies with substitutes |
JP2003505753A (en) | 1999-06-10 | 2003-02-12 | ペーアーツェーテー インフォルマツィオーンステヒノロギー ゲゼルシャフト ミット ベシュレンクテル ハフツング | Sequence division method in cell structure |
EP2226732A3 (en) * | 2000-06-13 | 2016-04-06 | PACT XPP Technologies AG | Cache hierarchy for a multicore processor |
US8058899B2 (en) | 2000-10-06 | 2011-11-15 | Martin Vorbach | Logic cell array and bus system |
US7595659B2 (en) * | 2000-10-09 | 2009-09-29 | Pact Xpp Technologies Ag | Logic cell array and bus system |
US7020673B2 (en) * | 2001-01-19 | 2006-03-28 | Sony Corporation | Reconfigurable arithmetic device and arithmetic system including that arithmetic device and address generation device and interleave device applicable to arithmetic system |
WO2005045692A2 (en) | 2003-08-28 | 2005-05-19 | Pact Xpp Technologies Ag | Data processing device and method |
US7844796B2 (en) | 2001-03-05 | 2010-11-30 | Martin Vorbach | Data processing device and method |
US9037807B2 (en) | 2001-03-05 | 2015-05-19 | Pact Xpp Technologies Ag | Processor arrangement on a chip including data processing, memory, and interface elements |
US7444531B2 (en) | 2001-03-05 | 2008-10-28 | Pact Xpp Technologies Ag | Methods and devices for treating and processing data |
US7581076B2 (en) * | 2001-03-05 | 2009-08-25 | Pact Xpp Technologies Ag | Methods and devices for treating and/or processing data |
US7453922B2 (en) * | 2001-03-14 | 2008-11-18 | Mercury Computer Systems, Inc. | Wireless communication systems and methods for contiguously addressable memory enabled multiple processor based multiple user detection |
US7376175B2 (en) * | 2001-03-14 | 2008-05-20 | Mercury Computer Systems, Inc. | Wireless communications systems and methods for cache enabled multiple processor based multiple user detection |
US7249242B2 (en) | 2002-10-28 | 2007-07-24 | Nvidia Corporation | Input pipeline registers for a node in an adaptive computing engine |
US6836839B2 (en) | 2001-03-22 | 2004-12-28 | Quicksilver Technology, Inc. | Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements |
US7962716B2 (en) | 2001-03-22 | 2011-06-14 | Qst Holdings, Inc. | Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements |
US7653710B2 (en) | 2002-06-25 | 2010-01-26 | Qst Holdings, Llc. | Hardware task manager |
US7752419B1 (en) | 2001-03-22 | 2010-07-06 | Qst Holdings, Llc | Method and system for managing hardware resources to implement system functions using an adaptive computing architecture |
US6577678B2 (en) | 2001-05-08 | 2003-06-10 | Quicksilver Technology | Method and system for reconfigurable channel coding |
AU2002347560A1 (en) | 2001-06-20 | 2003-01-02 | Pact Xpp Technologies Ag | Data processing method |
US7996827B2 (en) | 2001-08-16 | 2011-08-09 | Martin Vorbach | Method for the translation of programs for reconfigurable architectures |
US7434191B2 (en) | 2001-09-03 | 2008-10-07 | Pact Xpp Technologies Ag | Router |
US8686475B2 (en) | 2001-09-19 | 2014-04-01 | Pact Xpp Technologies Ag | Reconfigurable elements |
US7024441B2 (en) * | 2001-10-03 | 2006-04-04 | Intel Corporation | Performance optimized approach for efficient numerical computations |
US7046635B2 (en) | 2001-11-28 | 2006-05-16 | Quicksilver Technology, Inc. | System for authorizing functionality in adaptable hardware devices |
US6986021B2 (en) | 2001-11-30 | 2006-01-10 | Quick Silver Technology, Inc. | Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements |
US8412915B2 (en) | 2001-11-30 | 2013-04-02 | Altera Corporation | Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements |
US7215701B2 (en) | 2001-12-12 | 2007-05-08 | Sharad Sambhwani | Low I/O bandwidth method and system for implementing detection and identification of scrambling codes |
US7403981B2 (en) | 2002-01-04 | 2008-07-22 | Quicksilver Technology, Inc. | Apparatus and method for adaptive multimedia reception and transmission in communication environments |
DE10392560D2 (en) | 2002-01-19 | 2005-05-12 | Pact Xpp Technologies Ag | Reconfigurable processor |
AU2003214003A1 (en) | 2002-02-18 | 2003-09-09 | Pact Xpp Technologies Ag | Bus systems and method for reconfiguration |
US8914590B2 (en) | 2002-08-07 | 2014-12-16 | Pact Xpp Technologies Ag | Data processing method and device |
US7660984B1 (en) | 2003-05-13 | 2010-02-09 | Quicksilver Technology | Method and system for achieving individualized protected space in an operating system |
US7328414B1 (en) | 2003-05-13 | 2008-02-05 | Qst Holdings, Llc | Method and system for creating and programming an adaptive computing engine |
US7657861B2 (en) | 2002-08-07 | 2010-02-02 | Pact Xpp Technologies Ag | Method and device for processing data |
WO2004021176A2 (en) | 2002-08-07 | 2004-03-11 | Pact Xpp Technologies Ag | Method and device for processing data |
US8108656B2 (en) | 2002-08-29 | 2012-01-31 | Qst Holdings, Llc | Task definition for specifying resource requirements |
WO2004038599A1 (en) | 2002-09-06 | 2004-05-06 | Pact Xpp Technologies Ag | Reconfigurable sequencer structure |
US7353243B2 (en) * | 2002-10-22 | 2008-04-01 | Nvidia Corporation | Reconfigurable filter node for an adaptive computing machine |
US7937591B1 (en) | 2002-10-25 | 2011-05-03 | Qst Holdings, Llc | Method and system for providing a device which can be adapted on an ongoing basis |
US8276135B2 (en) | 2002-11-07 | 2012-09-25 | Qst Holdings Llc | Profiling of software and circuit designs utilizing data operation analyses |
US7225301B2 (en) | 2002-11-22 | 2007-05-29 | Quicksilver Technologies | External memory controller node |
US20050285935A1 (en) * | 2004-06-29 | 2005-12-29 | Octiv, Inc. | Personal conferencing node |
JP2009524134A (en) | 2006-01-18 | 2009-06-25 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | Hardware definition method |
US20080250092A1 (en) * | 2007-04-06 | 2008-10-09 | Technology Properties Limited | System for convolution calculation with multiple computer processors |
EP2413236A1 (en) * | 2010-07-29 | 2012-02-01 | Nxp B.V. | Partial averaging circuit and method |
US10581407B2 (en) * | 2018-05-08 | 2020-03-03 | The Boeing Company | Scalable fir filter |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4404645A (en) | 1980-08-18 | 1983-09-13 | Elings Virgil B | Correlator |
US4694416A (en) * | 1985-02-25 | 1987-09-15 | General Electric Company | VLSI programmable digital signal processor |
US4967340A (en) * | 1985-06-12 | 1990-10-30 | E-Systems, Inc. | Adaptive processing system having an array of individually configurable processing components |
JPH0740252B2 (en) * | 1986-03-08 | 1995-05-01 | 株式会社日立製作所 | Multi-processor system |
IT1227520B (en) | 1988-12-06 | 1991-04-12 | Sgs Thomson Microelectronics | PROGRAMMABLE DIGITAL FILTER |
US5477221A (en) | 1990-07-10 | 1995-12-19 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Pipeline synthetic aperture radar data compression utilizing systolic binary tree-searched architecture for vector quantization |
US5301344A (en) * | 1991-01-29 | 1994-04-05 | Analogic Corporation | Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of data sets |
JPH04293151A (en) * | 1991-03-20 | 1992-10-16 | Fujitsu Ltd | Parallel data processing system |
TW207013B (en) * | 1993-02-19 | 1993-06-01 | Nat Science Committee | Architecture of optimal high-speed sorter |
US5383145A (en) | 1993-10-14 | 1995-01-17 | Matsushita Electric Industrial Co., Ltd. | Digital filter and digital signal processing system |
DE4344157A1 (en) * | 1993-12-23 | 1995-06-29 | Philips Patentverwaltung | Radio |
US5566101A (en) | 1995-08-15 | 1996-10-15 | Sigmatel, Inc. | Method and apparatus for a finite impulse response filter processor |
US5657263A (en) * | 1995-08-28 | 1997-08-12 | Motorola, Inc. | Computer processor having a pipelined architecture which utilizes feedback and method of using same |
IL127134A (en) | 1996-03-04 | 2002-11-10 | Oren Semiconductor Ltd | Dsp apparatus |
US6148395A (en) * | 1996-05-17 | 2000-11-14 | Texas Instruments Incorporated | Shared floating-point unit in a single chip multiprocessor |
US5784306A (en) | 1996-06-28 | 1998-07-21 | Cirrus Logic, Inc. | Parallel multiply accumulate array circuit |
US5896304A (en) | 1996-07-12 | 1999-04-20 | General Electric Company | Low power parallel correlator for measuring correlation between digital signal segments |
WO1998006030A1 (en) * | 1996-08-07 | 1998-02-12 | Sun Microsystems | Multifunctional execution unit |
FR2776093A1 (en) | 1998-03-10 | 1999-09-17 | Philips Electronics Nv | PROGRAMMABLE PROCESSOR CIRCUIT PROVIDED WITH A RECONFIGURABLE MEMORY FOR PRODUCING A DIGITAL FILTER |
US6295545B1 (en) | 1998-11-12 | 2001-09-25 | Pc-Tel, Inc. | Reduction of execution times for convolution operations |
US6260053B1 (en) | 1998-12-09 | 2001-07-10 | Cirrus Logic, Inc. | Efficient and scalable FIR filter architecture for decimation |
US6738358B2 (en) * | 2000-09-09 | 2004-05-18 | Intel Corporation | Network echo canceller for integrated telecommunications processing |
-
2000
- 2000-08-07 US US09/633,831 patent/US6754805B1/en not_active Expired - Fee Related
-
2001
- 2001-08-06 WO PCT/US2001/024667 patent/WO2002012978A2/en active Application Filing
- 2001-08-06 AU AU2001279208A patent/AU2001279208A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
WO2002012978A3 (en) | 2002-05-23 |
US6754805B1 (en) | 2004-06-22 |
WO2002012978A2 (en) | 2002-02-14 |
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