AU2002227116A1 - Method and apparatus for physical budgeting during rtl floorplanning - Google Patents

Method and apparatus for physical budgeting during rtl floorplanning

Info

Publication number
AU2002227116A1
AU2002227116A1 AU2002227116A AU2711602A AU2002227116A1 AU 2002227116 A1 AU2002227116 A1 AU 2002227116A1 AU 2002227116 A AU2002227116 A AU 2002227116A AU 2711602 A AU2711602 A AU 2711602A AU 2002227116 A1 AU2002227116 A1 AU 2002227116A1
Authority
AU
Australia
Prior art keywords
floorplanning
budgeting
physical
during rtl
rtl
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002227116A
Inventor
Arnold Ginetti
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cadence Design Systems Inc
Original Assignee
Cadence Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cadence Design Systems Inc filed Critical Cadence Design Systems Inc
Publication of AU2002227116A1 publication Critical patent/AU2002227116A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation
AU2002227116A 2000-10-30 2001-10-30 Method and apparatus for physical budgeting during rtl floorplanning Abandoned AU2002227116A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09702090 2000-10-30
US09/702,090 US6622291B1 (en) 2000-10-30 2000-10-30 Method and apparatus for physical budgeting during RTL floorplanning
PCT/US2001/045441 WO2002037343A1 (en) 2000-10-30 2001-10-30 Method and apparatus for physical budgeting during rtl floorplanning

Publications (1)

Publication Number Publication Date
AU2002227116A1 true AU2002227116A1 (en) 2002-05-15

Family

ID=24819830

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002227116A Abandoned AU2002227116A1 (en) 2000-10-30 2001-10-30 Method and apparatus for physical budgeting during rtl floorplanning

Country Status (5)

Country Link
US (1) US6622291B1 (en)
EP (1) EP1330743A4 (en)
JP (1) JP2004513436A (en)
AU (1) AU2002227116A1 (en)
WO (1) WO2002037343A1 (en)

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US7721236B2 (en) * 2005-09-16 2010-05-18 Qualcomm Incorporated Method and apparatus of estimating circuit delay
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US7444605B2 (en) * 2005-10-06 2008-10-28 Synopsys, Inc. Generating a base curve database to reduce storage cost
US8402409B1 (en) 2006-03-10 2013-03-19 Xilinx, Inc. Method and apparatus for supporting run-time reconfiguration in a programmable logic integrated circuit
US7761272B1 (en) 2006-03-10 2010-07-20 Xilinx, Inc. Method and apparatus for processing a dataflow description of a digital processing system
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Also Published As

Publication number Publication date
EP1330743A4 (en) 2005-12-14
EP1330743A1 (en) 2003-07-30
WO2002037343A1 (en) 2002-05-10
JP2004513436A (en) 2004-04-30
WO2002037343A8 (en) 2002-07-11
US6622291B1 (en) 2003-09-16

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