AU2002225984A1 - Method and system for synchronizing an output signal to a data signal - Google Patents

Method and system for synchronizing an output signal to a data signal

Info

Publication number
AU2002225984A1
AU2002225984A1 AU2002225984A AU2598402A AU2002225984A1 AU 2002225984 A1 AU2002225984 A1 AU 2002225984A1 AU 2002225984 A AU2002225984 A AU 2002225984A AU 2598402 A AU2598402 A AU 2598402A AU 2002225984 A1 AU2002225984 A1 AU 2002225984A1
Authority
AU
Australia
Prior art keywords
synchronizing
output signal
data signal
signal
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002225984A
Inventor
Benjamin Tang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Primarion Inc
Original Assignee
Primarion Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Primarion Inc filed Critical Primarion Inc
Publication of AU2002225984A1 publication Critical patent/AU2002225984A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0996—Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
AU2002225984A 2000-11-13 2001-11-13 Method and system for synchronizing an output signal to a data signal Abandoned AU2002225984A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US24804300P 2000-11-13 2000-11-13
US60/248,043 2000-11-13
PCT/US2001/047025 WO2002039586A2 (en) 2000-11-13 2001-11-13 Method and system for synchronizing an output signal to a data signal

Publications (1)

Publication Number Publication Date
AU2002225984A1 true AU2002225984A1 (en) 2002-05-21

Family

ID=22937412

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002225984A Abandoned AU2002225984A1 (en) 2000-11-13 2001-11-13 Method and system for synchronizing an output signal to a data signal

Country Status (3)

Country Link
US (1) US6937685B2 (en)
AU (1) AU2002225984A1 (en)
WO (1) WO2002039586A2 (en)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050001661A1 (en) * 2002-10-29 2005-01-06 Zvi Regev Digital phase locked loop
US7489757B2 (en) * 2003-05-01 2009-02-10 Mitsubishi Denki Kabushiki Kaisha Clock data recovery circuit
JP4335586B2 (en) * 2003-06-11 2009-09-30 Ｎｅｃエレクトロニクス株式会社 Clock and data recovery circuit
JP4271623B2 (en) * 2004-06-17 2009-06-03 富士通株式会社 Clock adjustment apparatus and method
TWI242929B (en) * 2004-12-01 2005-11-01 Ind Tech Res Inst Clock and data recovery apparatus and method thereof
TWI263408B (en) * 2005-01-18 2006-10-01 Sunext Technology Co Ltd Digital frequency/phase recovery circuit
JP4928097B2 (en) * 2005-07-29 2012-05-09 株式会社アドバンテスト Timing generator and semiconductor test apparatus
US7864911B2 (en) * 2006-09-13 2011-01-04 Sony Corporation System and method for implementing a phase detector to support a data transmission procedure
US7675332B1 (en) * 2007-01-31 2010-03-09 Altera Corporation Fractional delay-locked loops
US7592846B2 (en) * 2007-02-16 2009-09-22 Intersil Americas Inc. Method for using digital PLL in a voltage regulator
KR100894486B1 (en) * 2007-11-02 2009-04-22 주식회사 하이닉스반도체 Digital filter, clock data recovery circuit and operation method thereof, semiconductor memory device and operation method thereof
US8095102B2 (en) * 2008-11-17 2012-01-10 Infineon Technologies Ag Phase-lock loop
CN102326443B (en) * 2008-12-23 2014-06-04 康奈尔大学 Systems and methods for PCO based UWB impulse radio with localized synchronization detection and retention
US8587351B1 (en) * 2012-05-11 2013-11-19 Hamilton Sundstrand Corporation Method for synchronizing sampling to sinusoidal inputs
US9184907B2 (en) * 2012-12-28 2015-11-10 Nvidia Corporation Flexible threshold counter for clock-and-data recovery
US8958513B1 (en) * 2013-03-15 2015-02-17 Xilinx, Inc. Clock and data recovery with infinite pull-in range
JP6476659B2 (en) * 2014-08-28 2019-03-06 富士通株式会社 Signal reproduction circuit and signal reproduction method
JP2018074375A (en) * 2016-10-28 2018-05-10 富士通株式会社 Clock regenerative circuit, semiconductor integrated circuit device and rf tag
US9998126B1 (en) * 2017-07-07 2018-06-12 Qualcomm Incorporated Delay locked loop (DLL) employing pulse to digital converter (PDC) for calibration
US10236897B1 (en) * 2018-07-26 2019-03-19 Texas Instruments Incorporated Loss of lock detector
KR20210042748A (en) * 2019-10-10 2021-04-20 삼성전자주식회사 A Phase-locked loop circuit and a clock generator including the same
CN115498999B (en) * 2022-09-16 2023-08-29 武汉市聚芯微电子有限责任公司 Phase tracking loop and method based on frequency division and clock acceleration and electronic equipment

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5463351A (en) * 1994-09-29 1995-10-31 Motorola, Inc. Nested digital phase lock loop
US5923704A (en) 1996-03-25 1999-07-13 Advanced Micro Devices, Inc. Transmit clock generation system and method
US5757297A (en) 1996-06-07 1998-05-26 International Business Machines Corporation Method and apparatus for recovering a serial data stream using a local clock
US5859881A (en) 1996-06-07 1999-01-12 International Business Machines Corporation Adaptive filtering method and apparatus to compensate for a frequency difference between two clock sources
CA2204089C (en) * 1997-04-30 2001-08-07 Mosaid Technologies Incorporated Digital delay locked loop
US6167526A (en) * 1998-12-29 2000-12-26 Adaptec, Inc. Method and apparatus for synchronizing a decoder circuit with a phase-encoded data signal in a data storage device

Also Published As

Publication number Publication date
WO2002039586A3 (en) 2003-02-13
US20020057118A1 (en) 2002-05-16
US6937685B2 (en) 2005-08-30
WO2002039586A2 (en) 2002-05-16

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