AU2001295903A1 - Module for generating circuits for decoding convolutional codes, related method and circuit - Google Patents

Module for generating circuits for decoding convolutional codes, related method and circuit

Info

Publication number
AU2001295903A1
AU2001295903A1 AU2001295903A AU9590301A AU2001295903A1 AU 2001295903 A1 AU2001295903 A1 AU 2001295903A1 AU 2001295903 A AU2001295903 A AU 2001295903A AU 9590301 A AU9590301 A AU 9590301A AU 2001295903 A1 AU2001295903 A1 AU 2001295903A1
Authority
AU
Australia
Prior art keywords
module
circuit
decoding circuits
related method
generating circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001295903A
Inventor
Gianmario Bollano
Donato Ettorre
Maura Turolla
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telecom Italia SpA
Original Assignee
Telecom Italia Lab SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telecom Italia Lab SpA filed Critical Telecom Italia Lab SpA
Publication of AU2001295903A1 publication Critical patent/AU2001295903A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding

Abstract

The present invention relates to a module 50 for generating integrated decoding circuits for use, in particular, in turbo devices, to the method for defining the characteristics of and generating convolutional decoding circuits, and to the circuit that can be obtained with said module 50. The module 50 is parametric and, thanks to this feature, makes it possible to generate decoding circuits having different performance characteristics which are such that they can be used in turbo devices employing different decoding modes and different architectures. In addition, the module 50 makes it possible to generate decoding circuits whose distinguishing feature is that they can manage a plurality of generator polynomials selectively and can thus also be used in asymmetrical turbo devices.
AU2001295903A 2000-10-19 2001-10-11 Module for generating circuits for decoding convolutional codes, related method and circuit Abandoned AU2001295903A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
ITTO00A000984 2000-10-19
IT2000TO000984A IT1320715B1 (en) 2000-10-19 2000-10-19 CIRCUIT GENERATOR MODULE FOR THE DECODING OF CONVENTIONAL CODES, METHOD FOR THE GENERATION OF SUCH TYPE OF CIRCUIT AND
PCT/IT2001/000514 WO2002033834A1 (en) 2000-10-19 2001-10-11 Module for generating circuits for decoding convolutional codes, related method and circuit

Publications (1)

Publication Number Publication Date
AU2001295903A1 true AU2001295903A1 (en) 2002-04-29

Family

ID=11458138

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001295903A Abandoned AU2001295903A1 (en) 2000-10-19 2001-10-11 Module for generating circuits for decoding convolutional codes, related method and circuit

Country Status (10)

Country Link
US (1) US7401284B2 (en)
EP (1) EP1336250B1 (en)
JP (1) JP3984162B2 (en)
KR (1) KR100855018B1 (en)
AT (1) ATE320112T1 (en)
AU (1) AU2001295903A1 (en)
DE (1) DE60117831T2 (en)
IT (1) IT1320715B1 (en)
RU (1) RU2298283C2 (en)
WO (1) WO2002033834A1 (en)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7376939B1 (en) * 2002-02-07 2008-05-20 Xilinx, Inc. System for architecture and resource specification and methods to compile the specification onto hardware
JP2004080508A (en) 2002-08-20 2004-03-11 Nec Electronics Corp Decoding method for error correction code, its program, and its device
NL1027012C2 (en) * 2004-09-10 2006-01-23 Tatung Co Reusable hardware IP protocol for system on a chip devices, determines whether hardware IP parameters are required and enters function parameter or search signal
FR2876472B1 (en) * 2004-10-08 2008-09-19 Tatung Co Ltd PROTOCOL METHOD FOR REUSABLE IP HARDWARE COMPONENT FOR A CHIP SYSTEM DEVICE
WO2009079242A2 (en) 2007-12-05 2009-06-25 Massachusetts Institute Of Technology Aglycosylated immunoglobulin mutants
US20110087949A1 (en) * 2008-06-09 2011-04-14 Nxp B.V. Reconfigurable turbo interleavers for multiple standards
US8406342B2 (en) 2008-06-19 2013-03-26 Qualcomm Incorporated Methods and systems for improving frame decoding performance using known information
EP2621954A1 (en) 2010-10-01 2013-08-07 Oxford Biotherapeutics Ltd. Anti-rori antibodies
JOP20210044A1 (en) 2010-12-30 2017-06-16 Takeda Pharmaceuticals Co Anti-cd38 antibodies
WO2013155346A1 (en) 2012-04-11 2013-10-17 The Regents Of The University Of California Diagnostic tools for response to 6-thiopurine therapy
US9260527B2 (en) 2013-03-15 2016-02-16 Sdix, Llc Anti-human CXCR4 antibodies and methods of making same
TWI527040B (en) * 2013-05-13 2016-03-21 群聯電子股份有限公司 Data writing method, memory storage device and memory controller
CN104182293B (en) * 2013-05-22 2017-06-30 群联电子股份有限公司 Method for writing data, memory storage apparatus and Memory Controller
DK3055331T3 (en) 2013-10-11 2021-03-22 Oxford Bio Therapeutics Ltd CONJUGATED ANTIBODIES TO LY75 FOR CANCER TREATMENT
MA45674A (en) 2016-07-15 2019-05-22 Takeda Pharmaceuticals Co METHODS AND MATERIALS FOR EVALUATING A RESPONSE TO PLASMOBLAST AND PLASMOCYTE DEPLÉTION TREATMENTS
RU2634201C1 (en) * 2016-07-26 2017-10-24 федеральное государственное казенное военное образовательное учреждение высшего образования "Краснодарское высшее военное училище имени генерала армии С.М. Штеменко" Министерства обороны Российской Федерации Device for spoofing resistant coding and decoding information with excessive systematic codes
GB201703876D0 (en) 2017-03-10 2017-04-26 Berlin-Chemie Ag Pharmaceutical combinations
CN112154156A (en) 2018-03-28 2020-12-29 武田药品工业株式会社 Subcutaneous administration of anti-CD 38 antibodies
GB201809746D0 (en) 2018-06-14 2018-08-01 Berlin Chemie Ag Pharmaceutical combinations
CN113993543A (en) 2019-06-10 2022-01-28 武田药品工业株式会社 Combination therapy with anti-CD 38 antibodies
WO2021259227A1 (en) 2020-06-23 2021-12-30 江苏康缘药业股份有限公司 Anti-cd38 antibody and use thereof
CN116406292A (en) 2020-10-09 2023-07-07 学校法人庆应义塾 Therapeutic agent for immune/inflammatory diseases

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6484283B2 (en) * 1998-12-30 2002-11-19 International Business Machines Corporation Method and apparatus for encoding and decoding a turbo code in an integrated modem system

Also Published As

Publication number Publication date
IT1320715B1 (en) 2003-12-10
KR20030063366A (en) 2003-07-28
EP1336250A1 (en) 2003-08-20
DE60117831T2 (en) 2006-12-14
US20040013210A1 (en) 2004-01-22
JP2004512726A (en) 2004-04-22
US7401284B2 (en) 2008-07-15
RU2298283C2 (en) 2007-04-27
DE60117831D1 (en) 2006-05-04
KR100855018B1 (en) 2008-08-28
EP1336250B1 (en) 2006-03-08
ITTO20000984A1 (en) 2002-04-19
ATE320112T1 (en) 2006-03-15
WO2002033834A1 (en) 2002-04-25
JP3984162B2 (en) 2007-10-03
ITTO20000984A0 (en) 2000-10-19
WO2002033834A9 (en) 2002-11-28

Similar Documents

Publication Publication Date Title
AU2001295903A1 (en) Module for generating circuits for decoding convolutional codes, related method and circuit
MXPA03011335A (en) Variable length encoding method and variable length decoding method.
TW200635239A (en) Fast compact decoder for huffman codes
DE60322715D1 (en) MIXED DENDRIMERE
CA2110244A1 (en) Extended List Output and Soft Symbol Output Viterbi Algorithms
WO2003021638A3 (en) High voltage integrated circuit amplifier
ATE298952T1 (en) LINEAR TRANSFORMATION FOR SYMMETRIC ENCRYPTION SYSTEMS
TW200742021A (en) Integrated circuit arrangement having a plurality of conductive structure levels and capacitor, and method
WO2002037687A3 (en) Method of performing huffman decoding
GB2377328A (en) Integrated circuit having various operational modes and a method therefor
WO2002019539A1 (en) Soft-output decoder
ATE550734T1 (en) CHIP CARD
ITRM20010522A1 (en) CONDITIONED AND STURDY "POWER-ON-RESET" SEQUENTIAL WITH ULTRA-LOW POWER FOR INTEGRATED CIRCUITS.
KR20020070743A (en) Bit level encoding/decoding method and apparatus
DE602005012060D1 (en) METHOD AND DEVICE FOR CARRYING OUT A CRYPTOGRAPHIC OPERATION
EP1542235A4 (en) Composite storage circuit and semiconductor device having the same composite storage circuit
ATE312431T1 (en) VOLTAGE CONTROLLED OSCILLATOR
WO2002052729A3 (en) Decoder, system and method for decoding turbo block codes
TW200713478A (en) Integrated circuit arrangement having a plurality of conductive structure levels and coil, and method
AU2003201054A8 (en) Circuits with improved power supply rejection
EP1160668A3 (en) Semiconductor integrated circuit and method of testing semiconductor integrated circuit
WO2003098811A8 (en) Memory for turbo decoder
HUP0203926A2 (en) Voltage level translation circuits
WO2003019564A3 (en) Magnetoresistive level generator
WO2005020064A3 (en) Hardware generator employing analog and digital correction circuits for generating uniform and gaussian distributed true random numbers