AU2001286970A1 - Planarization of metal container structures - Google Patents

Planarization of metal container structures

Info

Publication number
AU2001286970A1
AU2001286970A1 AU2001286970A AU8697001A AU2001286970A1 AU 2001286970 A1 AU2001286970 A1 AU 2001286970A1 AU 2001286970 A AU2001286970 A AU 2001286970A AU 8697001 A AU8697001 A AU 8697001A AU 2001286970 A1 AU2001286970 A1 AU 2001286970A1
Authority
AU
Australia
Prior art keywords
planarization
metal container
container structures
structures
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001286970A
Inventor
John M. Drynan
Sam Yang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of AU2001286970A1 publication Critical patent/AU2001286970A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
AU2001286970A 2000-08-31 2001-08-31 Planarization of metal container structures Abandoned AU2001286970A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/653,280 2000-08-31
US09/653,280 US6524912B1 (en) 2000-08-31 2000-08-31 Planarization of metal container structures
PCT/US2001/027138 WO2002019398A2 (en) 2000-08-31 2001-08-31 Planarization of metal container structures

Publications (1)

Publication Number Publication Date
AU2001286970A1 true AU2001286970A1 (en) 2002-03-13

Family

ID=24620202

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001286970A Abandoned AU2001286970A1 (en) 2000-08-31 2001-08-31 Planarization of metal container structures

Country Status (6)

Country Link
US (3) US6524912B1 (en)
JP (1) JP5093962B2 (en)
KR (1) KR100681088B1 (en)
CN (1) CN100347808C (en)
AU (1) AU2001286970A1 (en)
WO (1) WO2002019398A2 (en)

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US6511879B1 (en) 2000-06-16 2003-01-28 Micron Technology, Inc. Interconnect line selectively isolated from an underlying contact plug
US6524912B1 (en) * 2000-08-31 2003-02-25 Micron Technology, Inc. Planarization of metal container structures
KR100410981B1 (en) * 2001-05-18 2003-12-12 삼성전자주식회사 Metal Interconnection with Low Resistivity in Semiconductor Device and Method for Forming the Same
KR100386414B1 (en) * 2001-05-24 2003-06-09 엘지전자 주식회사 A speaker phone using in a mobile phone and method of removing a howling in a speaker phone
US20060060565A9 (en) * 2002-09-16 2006-03-23 Applied Materials, Inc. Method of etching metals with high selectivity to hafnium-based dielectric materials
JP2004200400A (en) * 2002-12-18 2004-07-15 Toshiba Corp Semiconductor device and manufacturing method thereof
KR100505450B1 (en) * 2002-12-26 2005-08-05 주식회사 하이닉스반도체 Method for fabricating semiconductor device using damascene process
US7125815B2 (en) * 2003-07-07 2006-10-24 Micron Technology, Inc. Methods of forming a phosphorous doped silicon dioxide comprising layer
US6962846B2 (en) * 2003-11-13 2005-11-08 Micron Technology, Inc. Methods of forming a double-sided capacitor or a contact using a sacrificial structure
US7053010B2 (en) * 2004-03-22 2006-05-30 Micron Technology, Inc. Methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation, and methods of forming arrays of memory cells
KR100648247B1 (en) 2004-06-07 2006-11-24 삼성전자주식회사 Method for forming metal lower electrode of a capacitor and selective metal etching method therefor
US7235459B2 (en) * 2004-08-31 2007-06-26 Micron Technology, Inc. Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry
US7312120B2 (en) * 2004-09-01 2007-12-25 Micron Technology, Inc. Method for obtaining extreme selectivity of metal nitrides and metal oxides
US7329576B2 (en) * 2004-09-02 2008-02-12 Micron Technology, Inc. Double-sided container capacitors using a sacrificial layer
US7510966B2 (en) * 2005-03-07 2009-03-31 Micron Technology, Inc. Electrically conductive line, method of forming an electrically conductive line, and method of reducing titanium silicide agglomeration in fabrication of titanium silicide over polysilicon transistor gate lines
US7445996B2 (en) * 2005-03-08 2008-11-04 Micron Technology, Inc. Low resistance peripheral contacts while maintaining DRAM array integrity
US8012847B2 (en) 2005-04-01 2011-09-06 Micron Technology, Inc. Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry
US8106438B2 (en) * 2005-08-22 2012-01-31 Micron Technology, Inc. Stud capacitor device and fabrication method
KR100661217B1 (en) * 2005-12-29 2006-12-22 동부일렉트로닉스 주식회사 Method of manufacturing semiconductor device
US20080125342A1 (en) * 2006-11-07 2008-05-29 Advanced Technology Materials, Inc. Formulations for cleaning memory device structures
US7884477B2 (en) * 2007-12-03 2011-02-08 International Business Machines Corporation Air gap structure having protective metal silicide pads on a metal feature
US8772939B2 (en) * 2008-08-04 2014-07-08 Micron Technology, Inc. Polishing systems and methods for removing conductive material from microelectronic substrates
US8753933B2 (en) 2008-11-19 2014-06-17 Micron Technology, Inc. Methods for forming a conductive material, methods for selectively forming a conductive material, methods for forming platinum, and methods for forming conductive structures
US8105956B2 (en) * 2009-10-20 2012-01-31 Micron Technology, Inc. Methods of forming silicon oxides and methods of forming interlevel dielectrics
JP2012156451A (en) * 2011-01-28 2012-08-16 Elpida Memory Inc Semiconductor device and method of manufacturing the same
US20120315754A1 (en) * 2011-06-08 2012-12-13 Micron Technology, Inc. Interconnection barrier material device and method
CN107833833B (en) * 2017-11-28 2020-01-21 上海华力微电子有限公司 Etching method for forming contact holes with different depths
US10636656B2 (en) * 2018-04-16 2020-04-28 Globalfoundries Inc. Methods of protecting structure of integrated circuit from rework
EP3958293B1 (en) * 2020-05-22 2024-06-12 Changxin Memory Technologies, Inc. Method for preparing a hole in a semiconductor device

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US5340370A (en) * 1993-11-03 1994-08-23 Intel Corporation Slurries for chemical mechanical polishing
JPH08139293A (en) * 1994-09-17 1996-05-31 Toshiba Corp Semiconductor substrate
US5600182A (en) * 1995-01-24 1997-02-04 Lsi Logic Corporation Barrier metal technology for tungsten plug interconnection
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Also Published As

Publication number Publication date
JP5093962B2 (en) 2012-12-12
CN100347808C (en) 2007-11-07
WO2002019398A3 (en) 2002-08-15
KR20030040435A (en) 2003-05-22
KR100681088B1 (en) 2007-02-08
US7053462B2 (en) 2006-05-30
CN1636262A (en) 2005-07-06
US20060170025A1 (en) 2006-08-03
US6524912B1 (en) 2003-02-25
WO2002019398A2 (en) 2002-03-07
JP2004508708A (en) 2004-03-18
US20030082903A1 (en) 2003-05-01

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