AU2001284738A1 - System and method for implementing a multi-level interrupt scheme in a computer system - Google Patents

System and method for implementing a multi-level interrupt scheme in a computer system

Info

Publication number
AU2001284738A1
AU2001284738A1 AU2001284738A AU8473801A AU2001284738A1 AU 2001284738 A1 AU2001284738 A1 AU 2001284738A1 AU 2001284738 A AU2001284738 A AU 2001284738A AU 8473801 A AU8473801 A AU 8473801A AU 2001284738 A1 AU2001284738 A1 AU 2001284738A1
Authority
AU
Australia
Prior art keywords
implementing
level interrupt
computer system
interrupt scheme
scheme
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001284738A
Inventor
Timothy C. Maleck
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=24874745&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=AU2001284738(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AU2001284738A1 publication Critical patent/AU2001284738A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
AU2001284738A 2000-11-17 2001-08-07 System and method for implementing a multi-level interrupt scheme in a computer system Abandoned AU2001284738A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/715,606 2000-11-17
US09/715,606 US6681281B1 (en) 2000-11-17 2000-11-17 System and method for implementing a multi-level interrupt scheme in a computer system
PCT/US2001/024690 WO2002041153A2 (en) 2000-11-17 2001-08-07 System and method for implementing a multi-level interrupt scheme in a computer system

Publications (1)

Publication Number Publication Date
AU2001284738A1 true AU2001284738A1 (en) 2002-05-27

Family

ID=24874745

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001284738A Abandoned AU2001284738A1 (en) 2000-11-17 2001-08-07 System and method for implementing a multi-level interrupt scheme in a computer system

Country Status (8)

Country Link
US (1) US6681281B1 (en)
EP (1) EP1336139A2 (en)
JP (1) JP4837235B2 (en)
KR (1) KR100847366B1 (en)
CN (1) CN1214332C (en)
AU (1) AU2001284738A1 (en)
TW (1) TWI289758B (en)
WO (1) WO2002041153A2 (en)

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US6766824B2 (en) 2001-12-20 2004-07-27 Koninklijke Philips Electronics N.V. Fluid control valve and a feedback control system therefor
US8595394B1 (en) 2003-06-26 2013-11-26 Nvidia Corporation Method and system for dynamic buffering of disk I/O command chains
KR100555501B1 (en) * 2003-06-26 2006-03-03 삼성전자주식회사 Dynamic bus arbitration method and bus aribotor
US8683132B1 (en) 2003-09-29 2014-03-25 Nvidia Corporation Memory controller for sequentially prefetching data for a processor of a computer system
US8356142B1 (en) 2003-11-12 2013-01-15 Nvidia Corporation Memory controller for non-sequentially prefetching data for a processor of a computer system
US8700808B2 (en) * 2003-12-01 2014-04-15 Nvidia Corporation Hardware support system for accelerated disk I/O
US7080179B1 (en) * 2004-03-26 2006-07-18 Foundry Networks, Inc. Multi-level interrupts
CN1969268B (en) * 2004-06-15 2010-05-26 Nxp股份有限公司 Host controller, bus communication device and method for operating the host controller
US8356143B1 (en) 2004-10-22 2013-01-15 NVIDIA Corporatin Prefetch mechanism for bus master memory access
CN101128808A (en) * 2005-02-28 2008-02-20 皇家飞利浦电子股份有限公司 Data processing system with interrupt controller and interrupt controlling method
US7627705B2 (en) * 2005-12-30 2009-12-01 Stmicroelectronics Pvt. Ltd. Method and apparatus for handling interrupts in embedded systems
US7788434B2 (en) * 2006-12-15 2010-08-31 Microchip Technology Incorporated Interrupt controller handling interrupts with and without coalescing
CN101526929B (en) * 2008-03-07 2012-08-29 深圳迈瑞生物医疗电子股份有限公司 Integrated-equipment driving system and application method thereof
US8356128B2 (en) * 2008-09-16 2013-01-15 Nvidia Corporation Method and system of reducing latencies associated with resource allocation by using multiple arbiters
US8370552B2 (en) * 2008-10-14 2013-02-05 Nvidia Corporation Priority based bus arbiters avoiding deadlock and starvation on buses that support retrying of transactions
US8698823B2 (en) 2009-04-08 2014-04-15 Nvidia Corporation System and method for deadlock-free pipelining
US8943252B2 (en) * 2012-08-16 2015-01-27 Microsoft Corporation Latency sensitive software interrupt and thread scheduling
US10078603B2 (en) 2012-11-30 2018-09-18 Red Hat Israel, Ltd. MSI events using dynamic memory monitoring
US9830286B2 (en) * 2013-02-14 2017-11-28 Red Hat Israel, Ltd. Event signaling in virtualized systems
CN103106113A (en) * 2013-02-25 2013-05-15 广东威创视讯科技股份有限公司 Interrupt event processing method and processing equipment

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59216254A (en) * 1983-05-25 1984-12-06 Hitachi Ltd Interruption level control system
JPS61267136A (en) 1985-05-22 1986-11-26 Toshiba Corp Interruption system for information processing system
US5125093A (en) * 1990-08-14 1992-06-23 Nexgen Microsystems Interrupt control for multiprocessor computer system
US5555420A (en) * 1990-12-21 1996-09-10 Intel Corporation Multiprocessor programmable interrupt controller system with separate interrupt bus and bus retry management
JPH04342052A (en) * 1991-05-17 1992-11-27 Yaskawa Electric Corp Arbitration circuit
US5392033A (en) * 1993-01-05 1995-02-21 International Business Machines Corporation Priority generator for providing controllable guaranteed fairness in accessing a shared bus
US5905898A (en) 1994-05-31 1999-05-18 Advanced Micro Devices, Inc. Apparatus and method for storing interrupt source information in an interrupt controller based upon interrupt priority
US5555430A (en) 1994-05-31 1996-09-10 Advanced Micro Devices Interrupt control architecture for symmetrical multiprocessing system
US5758105A (en) 1995-12-04 1998-05-26 International Business Machines Corporation Method and apparatus for bus arbitration between isochronous and non-isochronous devices
JP3208332B2 (en) * 1995-12-20 2001-09-10 インターナショナル・ビジネス・マシーンズ・コーポレーション Interrupt device
JPH09244991A (en) 1996-03-11 1997-09-19 Commuter Herikoputa Senshin Gijutsu Kenkyusho:Kk Distributed bus arbiter and bus arbitration method
US5918057A (en) 1997-03-20 1999-06-29 Industrial Technology Research Institute Method and apparatus for dispatching multiple interrupt requests simultaneously
JPH11232210A (en) 1998-02-16 1999-08-27 Fuji Xerox Co Ltd Information processor
JP3556465B2 (en) 1998-04-21 2004-08-18 株式会社ルネサステクノロジ Interrupt controller
US6041105A (en) * 1998-09-01 2000-03-21 Umax Data Systems Inc. Adapter circuitry for computers to support computer telephony
TW445422B (en) * 1999-10-06 2001-07-11 Via Tech Inc Software simulation testing system allowing the north bridge and south bridge to perform circuit tests respectively

Also Published As

Publication number Publication date
JP2004521410A (en) 2004-07-15
WO2002041153A2 (en) 2002-05-23
CN1474971A (en) 2004-02-11
TWI289758B (en) 2007-11-11
CN1214332C (en) 2005-08-10
JP4837235B2 (en) 2011-12-14
WO2002041153A3 (en) 2002-08-08
EP1336139A2 (en) 2003-08-20
KR20030051834A (en) 2003-06-25
KR100847366B1 (en) 2008-07-21
US6681281B1 (en) 2004-01-20

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