AU2001283559A1 - Circuits and sequences for enabling remote access to and control of non-adjacentcells - Google Patents

Circuits and sequences for enabling remote access to and control of non-adjacentcells

Info

Publication number
AU2001283559A1
AU2001283559A1 AU2001283559A AU8355901A AU2001283559A1 AU 2001283559 A1 AU2001283559 A1 AU 2001283559A1 AU 2001283559 A AU2001283559 A AU 2001283559A AU 8355901 A AU8355901 A AU 8355901A AU 2001283559 A1 AU2001283559 A1 AU 2001283559A1
Authority
AU
Australia
Prior art keywords
adjacentcells
sequences
circuits
control
remote access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001283559A
Inventor
Nicholas J. Macias
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of AU2001283559A1 publication Critical patent/AU2001283559A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
AU2001283559A 2000-10-31 2001-08-13 Circuits and sequences for enabling remote access to and control of non-adjacentcells Abandoned AU2001283559A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09702574 2000-10-31
US09/702,574 US6297667B1 (en) 2000-10-31 2000-10-31 Circuits and sequences for enabling remote access to and control of non-adjacent cells in a locally self-reconfigurable processing system composed of self-dual processing cells
PCT/US2001/041706 WO2002037682A1 (en) 2000-10-31 2001-08-13 Circuits and sequences for enabling remote access to and control of non-adjacent cells

Publications (1)

Publication Number Publication Date
AU2001283559A1 true AU2001283559A1 (en) 2002-05-15

Family

ID=24821783

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001283559A Abandoned AU2001283559A1 (en) 2000-10-31 2001-08-13 Circuits and sequences for enabling remote access to and control of non-adjacentcells

Country Status (3)

Country Link
US (1) US6297667B1 (en)
AU (1) AU2001283559A1 (en)
WO (1) WO2002037682A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6577159B1 (en) 2002-04-22 2003-06-10 Nicholas Jesse Macias Method and apparatus for automatic high-speed bypass routing in a cell matrix self-configurable hardware system
US7539967B1 (en) 2006-05-05 2009-05-26 Altera Corporation Self-configuring components on a device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5682107A (en) * 1994-04-01 1997-10-28 Xilinx, Inc. FPGA architecture with repeatable tiles including routing matrices and logic matrices
US6054871A (en) * 1997-12-12 2000-04-25 Xilinx, Inc. Method for self-reconfiguration of logic in a field programmable gate array
US6222381B1 (en) * 1999-12-31 2001-04-24 Lisa J. K. Durbeck Self-configurable parallel processing system made from self-dual code/data processing cells utilizing a non-shifting memory
US6255849B1 (en) * 2000-02-04 2001-07-03 Xilinx, Inc. On-chip self-modification for PLDs

Also Published As

Publication number Publication date
WO2002037682A1 (en) 2002-05-10
US6297667B1 (en) 2001-10-02

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