AU2001282486A1 - Method for providing bitwise constraints for test generation - Google Patents

Method for providing bitwise constraints for test generation

Info

Publication number
AU2001282486A1
AU2001282486A1 AU2001282486A AU8248601A AU2001282486A1 AU 2001282486 A1 AU2001282486 A1 AU 2001282486A1 AU 2001282486 A AU2001282486 A AU 2001282486A AU 8248601 A AU8248601 A AU 8248601A AU 2001282486 A1 AU2001282486 A1 AU 2001282486A1
Authority
AU
Australia
Prior art keywords
constraints
test generation
language
providing
bitwise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001282486A
Inventor
Guy Barruch
Vitaly Lagoon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cadence Design Israel II Ltd
Original Assignee
Verisity Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Verisity Ltd filed Critical Verisity Ltd
Publication of AU2001282486A1 publication Critical patent/AU2001282486A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318371—Methodologies therefor, e.g. algorithms, procedures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Debugging And Monitoring (AREA)
  • Traffic Control Systems (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Investigating Or Analysing Biological Materials (AREA)

Abstract

A method for enabling bitwise or bit slice constraints to be provided as part of the test generation process, by providing a language structure which enables these constraints to be expressed in a test generation language such as e code for example. The language structure for such bitwise constraints is then handled in a more flexible manner, such that the test generation process does not attempt to rigidly "solve" the expression containing the constraint as a function. Therefore, the propagation of constraints in such a structure do not necessarily need to be propagated from left to right, but instead are generated in a multi-directional manner. The language structure is particularly suitable for such operators as "[: ]", "|", "&", "^", "~", ">>" and "<<".
AU2001282486A 2000-08-28 2001-08-28 Method for providing bitwise constraints for test generation Abandoned AU2001282486A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US22808700P 2000-08-28 2000-08-28
US60/228,087 2000-08-28
PCT/IL2001/000803 WO2002019108A2 (en) 2000-08-28 2001-08-28 Method for providing bitwise constraints for test generation

Publications (1)

Publication Number Publication Date
AU2001282486A1 true AU2001282486A1 (en) 2002-03-13

Family

ID=22855730

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001282486A Abandoned AU2001282486A1 (en) 2000-08-28 2001-08-28 Method for providing bitwise constraints for test generation

Country Status (8)

Country Link
US (2) US6918076B2 (en)
EP (1) EP1314045B1 (en)
JP (1) JP4652663B2 (en)
AT (1) ATE295544T1 (en)
AU (1) AU2001282486A1 (en)
DE (1) DE60110811T2 (en)
IL (1) IL154585A0 (en)
WO (1) WO2002019108A2 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL154585A0 (en) 2000-08-28 2003-09-17 Verisity Ltd Method for providing bitwise constraints for test generation
US7318014B1 (en) * 2002-05-31 2008-01-08 Altera Corporation Bit accurate hardware simulation in system level simulators
US7991606B1 (en) 2003-04-01 2011-08-02 Altera Corporation Embedded logic analyzer functionality for system level environments
US7509246B1 (en) 2003-06-09 2009-03-24 Altera Corporation System level simulation models for hardware modules
US7225416B1 (en) * 2004-06-15 2007-05-29 Altera Corporation Methods and apparatus for automatic test component generation and inclusion into simulation testbench
US7434101B2 (en) * 2005-03-21 2008-10-07 International Business Machines Corporation Highly specialized scenarios in random test generation
US7627843B2 (en) * 2005-03-23 2009-12-01 International Business Machines Corporation Dynamically interleaving randomly generated test-cases for functional verification
DE102005036321A1 (en) * 2005-07-29 2007-02-01 Siemens Ag Test scenarios generating method for e.g. computer tomography system, involves determining dependences between individual processing steps and/or classes of steps, and generating scenarios based on selection of steps, classes or rules
US20070113219A1 (en) * 2005-11-17 2007-05-17 Microsoft Corporation Representing simulation values of variable in sharpley limited time and space
US9218271B2 (en) * 2011-10-04 2015-12-22 International Business Machines Corporation Test planning based on dynamic coverage analysis
US9720792B2 (en) 2012-08-28 2017-08-01 Synopsys, Inc. Information theoretic caching for dynamic problem generation in constraint solving
US11468218B2 (en) 2012-08-28 2022-10-11 Synopsys, Inc. Information theoretic subgraph caching
US8904320B2 (en) 2013-03-13 2014-12-02 Synopsys, Inc. Solving multiplication constraints by factorization
US9298592B2 (en) 2013-03-14 2016-03-29 International Business Machines Corporation Testing a software interface for a streaming hardware device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2820701B2 (en) * 1988-12-06 1998-11-05 三菱電機株式会社 Conversion method to binary
JPH064330A (en) * 1992-06-23 1994-01-14 Nec Corp Test system
GB9624935D0 (en) * 1996-11-29 1997-01-15 Sgs Thomson Microelectronics System and method for representing physical environment
US6182258B1 (en) * 1997-06-03 2001-01-30 Verisity Ltd. Method and apparatus for test generation during circuit design
US5832418A (en) * 1997-06-23 1998-11-03 Micron Electronics Apparatus for testing a controller with random contraints
WO2000028391A2 (en) * 1998-11-09 2000-05-18 Luk Lamellen Und Kupplungsbau Gmbh Motor vehicle
WO2001093084A1 (en) * 2000-06-02 2001-12-06 Johnson Joseph E Apparatus and method for handling logical and numerical uncertainty utilizing novel underlying precepts
IL154585A0 (en) * 2000-08-28 2003-09-17 Verisity Ltd Method for providing bitwise constraints for test generation

Also Published As

Publication number Publication date
ATE295544T1 (en) 2005-05-15
EP1314045A2 (en) 2003-05-28
US20020049944A1 (en) 2002-04-25
JP2004507833A (en) 2004-03-11
US20050203720A1 (en) 2005-09-15
WO2002019108A8 (en) 2004-04-29
IL154585A0 (en) 2003-09-17
WO2002019108A3 (en) 2002-07-25
US7613973B2 (en) 2009-11-03
DE60110811D1 (en) 2005-06-16
EP1314045B1 (en) 2005-05-11
US6918076B2 (en) 2005-07-12
DE60110811T2 (en) 2006-02-02
JP4652663B2 (en) 2011-03-16
WO2002019108A2 (en) 2002-03-07

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