AU2001277678A1 - Method and system for verifying modules destined for generating circuits - Google Patents

Method and system for verifying modules destined for generating circuits

Info

Publication number
AU2001277678A1
AU2001277678A1 AU2001277678A AU7767801A AU2001277678A1 AU 2001277678 A1 AU2001277678 A1 AU 2001277678A1 AU 2001277678 A AU2001277678 A AU 2001277678A AU 7767801 A AU7767801 A AU 7767801A AU 2001277678 A1 AU2001277678 A1 AU 2001277678A1
Authority
AU
Australia
Prior art keywords
generating circuits
destined
verifying
verifying modules
modules destined
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001277678A
Inventor
Gianmario Bollano
Donato Ettorre
Maura Turolla
Marcello Valentini
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telecom Italia SpA
Original Assignee
Telecom Italia Lab SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from IT2000TO000722A external-priority patent/IT1320549B1/en
Priority claimed from IT2000TO000981A external-priority patent/IT1320712B1/en
Application filed by Telecom Italia Lab SpA filed Critical Telecom Italia Lab SpA
Publication of AU2001277678A1 publication Critical patent/AU2001277678A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
AU2001277678A 2000-07-21 2001-07-17 Method and system for verifying modules destined for generating circuits Abandoned AU2001277678A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
ITTO2000A000722 2000-07-21
IT2000TO000722A IT1320549B1 (en) 2000-07-21 2000-07-21 Verifying circuit generation modules by converting synthesizable description of modules into high-level programming language
IT2000TO000981A IT1320712B1 (en) 2000-10-19 2000-10-19 Verifying circuit generation modules by converting synthesizable description of modules into high-level programming language
ITTO2000A000981 2000-10-19
PCT/IT2001/000378 WO2002008966A2 (en) 2000-07-21 2001-07-17 Method and system for verifying modules destined for generating circuits

Publications (1)

Publication Number Publication Date
AU2001277678A1 true AU2001277678A1 (en) 2002-02-05

Family

ID=26332867

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001277678A Abandoned AU2001277678A1 (en) 2000-07-21 2001-07-17 Method and system for verifying modules destined for generating circuits

Country Status (4)

Country Link
US (1) US20030154465A1 (en)
EP (1) EP1301875A2 (en)
AU (1) AU2001277678A1 (en)
WO (1) WO2002008966A2 (en)

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US7124376B2 (en) * 2000-05-02 2006-10-17 Palmchip Corporation Design tool for systems-on-a-chip
KR100448897B1 (en) * 2002-05-20 2004-09-16 삼성전자주식회사 Chip development system having function library
US7318014B1 (en) * 2002-05-31 2008-01-08 Altera Corporation Bit accurate hardware simulation in system level simulators
FR2843214B1 (en) 2002-07-30 2008-07-04 Bull Sa METHOD FOR FUNCTIONALLY CHECKING AN INTEGRATED CIRCUIT MODEL TO CONSTITUTE A VERIFICATION PLATFORM, EMULATOR EQUIPMENT AND VERIFICATION PLATFORM.
US7991606B1 (en) 2003-04-01 2011-08-02 Altera Corporation Embedded logic analyzer functionality for system level environments
JP4175953B2 (en) * 2003-05-23 2008-11-05 シャープ株式会社 High-level synthesis apparatus, hardware verification model generation method, hardware verification method, control program, and readable recording medium
US7044390B2 (en) * 2003-06-02 2006-05-16 Stmicroelectronics, Inc. Smart card emulator and related methods using buffering interface
US7509246B1 (en) 2003-06-09 2009-03-24 Altera Corporation System level simulation models for hardware modules
US7340727B2 (en) * 2004-01-27 2008-03-04 Broadcom Corporation Verilog to C++ language translator
US7225416B1 (en) * 2004-06-15 2007-05-29 Altera Corporation Methods and apparatus for automatic test component generation and inclusion into simulation testbench
US7684968B1 (en) * 2004-12-09 2010-03-23 Xilinx, Inc. Generation of a high-level simulation model of an electronic system by combining an HDL control function translated to a high-level language and a separate high-level data path function
WO2007066321A1 (en) 2005-12-08 2007-06-14 Mentor Graphics Corporation Transaction-based power model in circuit designs
US7673259B2 (en) * 2005-12-30 2010-03-02 Cadence Design Systems, Inc. System and method for synthesis reuse
US20070162268A1 (en) * 2006-01-12 2007-07-12 Bhaskar Kota Algorithmic electronic system level design platform
US20070162531A1 (en) * 2006-01-12 2007-07-12 Bhaskar Kota Flow transform for integrated circuit design and simulation having combined data flow, control flow, and memory flow views
US8135571B2 (en) * 2008-08-14 2012-03-13 International Business Machines Corporation Validating manufacturing test rules pertaining to an electronic component
US8065641B2 (en) * 2008-09-02 2011-11-22 International Business Machines Corporation Automatically creating manufacturing test rules pertaining to an electronic component
KR101910933B1 (en) * 2011-12-21 2018-10-24 에스케이하이닉스 주식회사 Semiconductor integrated circuit and control method of testing the same
US9996637B2 (en) * 2015-07-30 2018-06-12 International Business Machines Corporation Method for verifying hardware/software co-designs
US10409321B2 (en) 2017-02-03 2019-09-10 Raytheon Company Simulation system with clock and messaging synchronization

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH113367A (en) * 1997-03-14 1999-01-06 Interuniv Micro Electron Centrum Vzw Design environment and method for generating implementable description in digital system
US6606588B1 (en) * 1997-03-14 2003-08-12 Interuniversitair Micro-Elecktronica Centrum (Imec Vzw) Design apparatus and a method for generating an implementable description of a digital system
US6053947A (en) * 1997-05-31 2000-04-25 Lucent Technologies, Inc. Simulation model using object-oriented programming
US5920830A (en) * 1997-07-09 1999-07-06 General Electric Company Methods and apparatus for generating test vectors and validating ASIC designs
US6862563B1 (en) * 1998-10-14 2005-03-01 Arc International Method and apparatus for managing the configuration and functionality of a semiconductor design
JP2000123061A (en) * 1998-10-16 2000-04-28 Matsushita Electric Ind Co Ltd Database and method for designing integrated circuit device
US6678645B1 (en) * 1999-10-28 2004-01-13 Advantest Corp. Method and apparatus for SoC design validation
US6467075B1 (en) * 2000-03-24 2002-10-15 Nec Corporation Resolution of dynamic memory allocation/deallocation and pointers

Also Published As

Publication number Publication date
US20030154465A1 (en) 2003-08-14
WO2002008966A2 (en) 2002-01-31
WO2002008966A3 (en) 2003-01-09
EP1301875A2 (en) 2003-04-16

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