AU2001275973A1 - Post deposition sputtering - Google Patents

Post deposition sputtering

Info

Publication number
AU2001275973A1
AU2001275973A1 AU2001275973A AU7597301A AU2001275973A1 AU 2001275973 A1 AU2001275973 A1 AU 2001275973A1 AU 2001275973 A AU2001275973 A AU 2001275973A AU 7597301 A AU7597301 A AU 7597301A AU 2001275973 A1 AU2001275973 A1 AU 2001275973A1
Authority
AU
Australia
Prior art keywords
post deposition
deposition sputtering
sputtering
post
deposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001275973A
Inventor
Valli Arunachalam
Dean J. Denning
Shahid Rauf
Peter L. G. Ventzek
Jiming Zhang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of AU2001275973A1 publication Critical patent/AU2001275973A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76862—Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
AU2001275973A 2000-07-21 2001-07-18 Post deposition sputtering Abandoned AU2001275973A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US62177300A 2000-07-21 2000-07-21
US09621773 2000-07-21
PCT/US2001/022566 WO2002009149A2 (en) 2000-07-21 2001-07-18 Post deposition sputtering

Publications (1)

Publication Number Publication Date
AU2001275973A1 true AU2001275973A1 (en) 2002-02-05

Family

ID=24491571

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001275973A Abandoned AU2001275973A1 (en) 2000-07-21 2001-07-18 Post deposition sputtering

Country Status (3)

Country Link
AU (1) AU2001275973A1 (en)
TW (1) TW504756B (en)
WO (1) WO2002009149A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004063556A (en) * 2002-07-25 2004-02-26 Matsushita Electric Ind Co Ltd Semiconductor device fabricating process
TWI435386B (en) * 2009-07-21 2014-04-21 Ulvac Inc Method of processing film surface
CN102820255A (en) * 2011-06-08 2012-12-12 无锡华润上华半导体有限公司 Method for physics vapor deposition (PVD) film
US11162170B2 (en) 2014-02-06 2021-11-02 Applied Materials, Inc. Methods for reducing material overhang in a feature of a substrate
US9666516B2 (en) 2014-12-01 2017-05-30 General Electric Company Electronic packages and methods of making and using the same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2602276B2 (en) * 1987-06-30 1997-04-23 株式会社日立製作所 Sputtering method and apparatus
US5929526A (en) * 1997-06-05 1999-07-27 Micron Technology, Inc. Removal of metal cusp for improved contact fill
US6077779A (en) * 1998-05-22 2000-06-20 Taiwan Semiconductor Manufacturing Company Multi-step deposition to improve the conformality of ionized PVD films
US6187682B1 (en) * 1998-05-26 2001-02-13 Motorola Inc. Inert plasma gas surface cleaning process performed insitu with physical vapor deposition (PVD) of a layer of material
US6124203A (en) * 1998-12-07 2000-09-26 Advanced Micro Devices, Inc. Method for forming conformal barrier layers
US6228754B1 (en) * 1999-01-05 2001-05-08 Advanced Micro Devices, Inc. Method for forming semiconductor seed layers by inert gas sputter etching

Also Published As

Publication number Publication date
WO2002009149A3 (en) 2002-05-16
TW504756B (en) 2002-10-01
WO2002009149A2 (en) 2002-01-31

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