AU2001275272A1 - Formation of self-aligned passivation for interconnect to minimize electromigration - Google Patents

Formation of self-aligned passivation for interconnect to minimize electromigration

Info

Publication number
AU2001275272A1
AU2001275272A1 AU2001275272A AU7527201A AU2001275272A1 AU 2001275272 A1 AU2001275272 A1 AU 2001275272A1 AU 2001275272 A AU2001275272 A AU 2001275272A AU 7527201 A AU7527201 A AU 7527201A AU 2001275272 A1 AU2001275272 A1 AU 2001275272A1
Authority
AU
Australia
Prior art keywords
interconnect
self
formation
minimize electromigration
passivation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001275272A
Inventor
Joffre Bernard
Amit Marathe
Pin-Chin C. Wang
Lu You
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AU2001275272A1 publication Critical patent/AU2001275272A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
AU2001275272A 2000-08-03 2001-06-04 Formation of self-aligned passivation for interconnect to minimize electromigration Abandoned AU2001275272A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/630,943 2000-08-03
US09/630,943 US6309959B1 (en) 2000-08-03 2000-08-03 Formation of self-aligned passivation for interconnect to minimize electromigration
PCT/US2001/018227 WO2002013233A2 (en) 2000-08-03 2001-06-04 Formation of self-aligned passivation for interconnect to minimize electromigration

Publications (1)

Publication Number Publication Date
AU2001275272A1 true AU2001275272A1 (en) 2002-02-18

Family

ID=24529205

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001275272A Abandoned AU2001275272A1 (en) 2000-08-03 2001-06-04 Formation of self-aligned passivation for interconnect to minimize electromigration

Country Status (5)

Country Link
US (1) US6309959B1 (en)
EP (1) EP1317770A2 (en)
AU (1) AU2001275272A1 (en)
TW (1) TW492090B (en)
WO (1) WO2002013233A2 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6432753B1 (en) * 2001-04-23 2002-08-13 Texas Instruments Incorporated Method of minimizing package-shift effects in integrated circuits by using a thick metallic overcoat
US6432822B1 (en) * 2001-05-02 2002-08-13 Advanced Micro Devices, Inc. Method of improving electromigration resistance of capped Cu
US6429128B1 (en) * 2001-07-12 2002-08-06 Advanced Micro Devices, Inc. Method of forming nitride capped Cu lines with reduced electromigration along the Cu/nitride interface
US6911394B2 (en) 2002-02-25 2005-06-28 Texas Instruments Incorporated Semiconductor devices and methods of manufacturing such semiconductor devices
US7163901B2 (en) * 2002-03-13 2007-01-16 Varian Semiconductor Equipment Associates, Inc. Methods for forming thin film layers by simultaneous doping and sintering
US6720204B2 (en) * 2002-04-11 2004-04-13 Chartered Semiconductor Manufacturing Ltd. Method of using hydrogen plasma to pre-clean copper surfaces during Cu/Cu or Cu/metal bonding
DE102004003863B4 (en) * 2004-01-26 2009-01-29 Advanced Micro Devices, Inc., Sunnyvale Technique for making embedded metal lines with increased resistance to stress-induced material transport
DE102004021239B4 (en) * 2004-04-30 2017-04-06 Infineon Technologies Ag Long annealed integrated circuit arrangements and their manufacturing processes
US8188600B2 (en) * 2004-06-24 2012-05-29 Nec Corporation Semiconductor device and method of fabricating the same
DE102005057075B4 (en) * 2005-11-30 2012-04-26 Advanced Micro Devices, Inc. Semiconductor device having a copper alloy as a barrier layer in a Kupfermetallisierungsschicht and method for its preparation
WO2012085987A1 (en) * 2010-12-24 2012-06-28 パナソニック株式会社 Method for producing semiconductor transistor, drive circuit using semiconductor transistor produced by said method, pixel circuit including said drive circuit and display element, display panel having said pixel circuits arranged in a matrix, and display device including said panel
US9252094B2 (en) * 2011-04-30 2016-02-02 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure with conductive material recessed within conductive ring over surface of conductive pillar
KR101872949B1 (en) * 2011-05-17 2018-07-02 삼성전자주식회사 Phase change memory device and method of manufacturing the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5766379A (en) * 1995-06-07 1998-06-16 The Research Foundation Of State University Of New York Passivated copper conductive layers for microelectronic applications and methods of manufacturing same
DE69637333T2 (en) * 1995-06-27 2008-10-02 International Business Machines Corp. Copper alloys for chip connections and manufacturing processes
US6268291B1 (en) * 1995-12-29 2001-07-31 International Business Machines Corporation Method for forming electromigration-resistant structures by doping
US5913147A (en) * 1997-01-21 1999-06-15 Advanced Micro Devices, Inc. Method for fabricating copper-aluminum metallization
US6181012B1 (en) * 1998-04-27 2001-01-30 International Business Machines Corporation Copper interconnection structure incorporating a metal seed layer
US6218302B1 (en) * 1998-07-21 2001-04-17 Motorola Inc. Method for forming a semiconductor device
US20010049181A1 (en) * 1998-11-17 2001-12-06 Sudha Rathi Plasma treatment for cooper oxide reduction
KR100385042B1 (en) * 1998-12-03 2003-06-18 인터내셔널 비지네스 머신즈 코포레이션 Method for forming electromigration-resistant structures by doping
US6228759B1 (en) * 2000-05-02 2001-05-08 Advanced Micro Devices, Inc. Method of forming an alloy precipitate to surround interconnect to minimize electromigration
US6261963B1 (en) * 2000-07-07 2001-07-17 Advanced Micro Devices, Inc. Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices

Also Published As

Publication number Publication date
EP1317770A2 (en) 2003-06-11
US6309959B1 (en) 2001-10-30
WO2002013233A2 (en) 2002-02-14
TW492090B (en) 2002-06-21
WO2002013233A3 (en) 2002-08-08

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