AU2001269217A1 - Method for converting the binary representation of a number in a signed binary representation - Google Patents
Method for converting the binary representation of a number in a signed binary representationInfo
- Publication number
- AU2001269217A1 AU2001269217A1 AU2001269217A AU6921701A AU2001269217A1 AU 2001269217 A1 AU2001269217 A1 AU 2001269217A1 AU 2001269217 A AU2001269217 A AU 2001269217A AU 6921701 A AU6921701 A AU 6921701A AU 2001269217 A1 AU2001269217 A1 AU 2001269217A1
- Authority
- AU
- Australia
- Prior art keywords
- binary representation
- converting
- signed
- signed binary
- representation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/02—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word
- H03M7/12—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word having two radices, e.g. binary-coded-decimal code
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
- G06F7/5332—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by skipping over strings of zeroes or ones, e.g. using the Booth Algorithm
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0008547 | 2000-06-30 | ||
FR0008547A FR2811168B1 (en) | 2000-06-30 | 2000-06-30 | METHOD FOR CONVERTING THE BINARY REPRESENTATION OF A NUMBER IN A SIGNED BINARY REPRESENTATION |
PCT/FR2001/001944 WO2002001727A1 (en) | 2000-06-30 | 2001-06-20 | Method for converting the binary representation of a number in a signed binary representation |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2001269217A1 true AU2001269217A1 (en) | 2002-01-08 |
Family
ID=8851988
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2001269217A Abandoned AU2001269217A1 (en) | 2000-06-30 | 2001-06-20 | Method for converting the binary representation of a number in a signed binary representation |
Country Status (6)
Country | Link |
---|---|
US (1) | US6903663B2 (en) |
EP (1) | EP1299953A1 (en) |
CN (1) | CN1258883C (en) |
AU (1) | AU2001269217A1 (en) |
FR (1) | FR2811168B1 (en) |
WO (1) | WO2002001727A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4682852B2 (en) * | 2006-01-16 | 2011-05-11 | ソニー株式会社 | Cryptographic processing apparatus, cryptographic processing method, and computer program |
US7996798B2 (en) * | 2007-05-24 | 2011-08-09 | Microsoft Corporation | Representing binary code as a circuit |
EP2169535A1 (en) * | 2008-09-22 | 2010-03-31 | Thomson Licensing | Method, apparatus and computer program support for regular recoding of a positive integer |
US8812570B2 (en) * | 2009-05-28 | 2014-08-19 | Red Hat, Inc. | String hashing using a number generator |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6053907B2 (en) * | 1978-01-27 | 1985-11-27 | 日本電気株式会社 | Binomial vector multiplication circuit |
DE4308112A1 (en) * | 1993-03-15 | 1994-10-13 | Andreas Herrfeld | Circuit for the CSD [canonical signed digit] encoding of a binary two's complement or binary number |
US6263081B1 (en) * | 1997-07-17 | 2001-07-17 | Matsushita Electric Industrial Co., Ltd. | Elliptic curve calculation apparatus capable of calculating multiples at high speed |
-
2000
- 2000-06-30 FR FR0008547A patent/FR2811168B1/en not_active Expired - Fee Related
-
2001
- 2001-06-20 AU AU2001269217A patent/AU2001269217A1/en not_active Abandoned
- 2001-06-20 US US10/312,530 patent/US6903663B2/en not_active Expired - Fee Related
- 2001-06-20 CN CN01812126.8A patent/CN1258883C/en not_active Expired - Fee Related
- 2001-06-20 EP EP01947558A patent/EP1299953A1/en not_active Withdrawn
- 2001-06-20 WO PCT/FR2001/001944 patent/WO2002001727A1/en active Search and Examination
Also Published As
Publication number | Publication date |
---|---|
FR2811168B1 (en) | 2002-11-15 |
US20040215684A1 (en) | 2004-10-28 |
CN1258883C (en) | 2006-06-07 |
EP1299953A1 (en) | 2003-04-09 |
FR2811168A1 (en) | 2002-01-04 |
CN1440591A (en) | 2003-09-03 |
US6903663B2 (en) | 2005-06-07 |
WO2002001727A1 (en) | 2002-01-03 |
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