AU2001264757A1 - Dual-ported cams for a simultaneous operation flash memory - Google Patents

Dual-ported cams for a simultaneous operation flash memory

Info

Publication number
AU2001264757A1
AU2001264757A1 AU2001264757A AU6475701A AU2001264757A1 AU 2001264757 A1 AU2001264757 A1 AU 2001264757A1 AU 2001264757 A AU2001264757 A AU 2001264757A AU 6475701 A AU6475701 A AU 6475701A AU 2001264757 A1 AU2001264757 A1 AU 2001264757A1
Authority
AU
Australia
Prior art keywords
cam
cell
memory
memory cell
flash memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001264757A
Inventor
Ali Al-Shamma
Lee Cleveland
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AU2001264757A1 publication Critical patent/AU2001264757A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G11C15/046—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements using non-volatile storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A flash memory having redundancy content addressable memory (CAM) circuitry is described. The flash memory is capable of substituting a second memory cell for an inoperative memory cell. The flash memory includes a primary array of memory cells, a redundant array of memory cells, and the redundancy CAM circuitry. The redundancy CAM circuitry includes a plurality of dual-ported CAM stages. Each CAM stage includes a CAM cell, a write data bus coupled to the CAM cell, and a read data bus coupled to the CAM cell. The CAM cell stores information regarding a location of an inoperative memory cell in the primary array. The inoperative memory cell requires a substitution with a second memory cell in the redundant array. The write data bus produces the information from the CAM cell responsively to a write select signal. The write select signal is indicative of a write operation to be performed at memory cell locations in the primary array. The read data bus produces the information from the CAM cell responsively to a read select signal. The read select signal is indicative of a read operation to be performed at memory cell locations in the primary array.
AU2001264757A 2000-05-31 2001-05-21 Dual-ported cams for a simultaneous operation flash memory Abandoned AU2001264757A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US20844900P 2000-05-31 2000-05-31
US60208449 2000-05-31
US09/829,657 US6396749B2 (en) 2000-05-31 2001-04-10 Dual-ported CAMs for a simultaneous operation flash memory
US09829657 2001-04-10
PCT/US2001/016393 WO2001093034A2 (en) 2000-05-31 2001-05-21 Dual-ported cams for a simultaneous operation flash memory

Publications (1)

Publication Number Publication Date
AU2001264757A1 true AU2001264757A1 (en) 2001-12-11

Family

ID=26903205

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001264757A Abandoned AU2001264757A1 (en) 2000-05-31 2001-05-21 Dual-ported cams for a simultaneous operation flash memory

Country Status (11)

Country Link
US (1) US6396749B2 (en)
EP (1) EP1290559B1 (en)
JP (1) JP4606694B2 (en)
KR (1) KR100915450B1 (en)
CN (1) CN1204497C (en)
AT (1) ATE262700T1 (en)
AU (1) AU2001264757A1 (en)
BR (1) BR0111245A (en)
DE (1) DE60102466T2 (en)
TW (1) TW587255B (en)
WO (1) WO2001093034A2 (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6492881B2 (en) * 2001-01-31 2002-12-10 Compaq Information Technologies Group, L.P. Single to differential logic level interface for computer systems
US6711720B2 (en) * 2002-03-14 2004-03-23 Hewlett-Packard Development Company, L.P. Method of optimizing high performance CMOS integrated circuit designs for power consumption and speed through genetic optimization
US6745371B2 (en) * 2002-03-15 2004-06-01 Sun Microsystems, Inc. Low Vt transistor substitution in a semiconductor device
US6845025B1 (en) 2003-03-21 2005-01-18 Netlogic Microsystems, Inc. Word line driver circuit for a content addressable memory
US7032200B1 (en) 2003-09-09 2006-04-18 Sun Microsystems, Inc. Low threshold voltage transistor displacement in a semiconductor device
US6973003B1 (en) 2003-10-01 2005-12-06 Advanced Micro Devices, Inc. Memory device and method
US7200693B2 (en) * 2004-08-27 2007-04-03 Micron Technology, Inc. Memory system and method having unidirectional data buses
US7209405B2 (en) 2005-02-23 2007-04-24 Micron Technology, Inc. Memory device and method having multiple internal data buses and memory bank interleaving
US20070028027A1 (en) * 2005-07-26 2007-02-01 Micron Technology, Inc. Memory device and method having separate write data and read data buses
US7301832B2 (en) * 2005-11-03 2007-11-27 Atmel Corporation Compact column redundancy CAM architecture for concurrent read and write operations in multi-segment memory arrays
US7567448B2 (en) * 2007-01-05 2009-07-28 Atmel Corporation Content addressable memory cell having a single floating gate transistor
JP2008234806A (en) * 2007-03-23 2008-10-02 Toshiba Corp Semiconductor memory device and its redundancy method
US9727452B2 (en) * 2007-12-14 2017-08-08 Virident Systems, Llc Distributing metadata across multiple different disruption regions within an asymmetric memory system
US7996736B2 (en) * 2008-10-26 2011-08-09 Sandisk 3D Llc Bad page marking strategy for fast readout in memory
US7911818B2 (en) * 2009-03-16 2011-03-22 Netlogic Microsystems, Inc. Content addressable memory having bidirectional lines that support passing read/write data and search data
US20140115422A1 (en) 2012-10-24 2014-04-24 Laurence H. Cooke Non-volatile memory error correction

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02282999A (en) * 1989-04-25 1990-11-20 Oki Micro Design Miyazaki:Kk Semiconductor memory device
US5245572A (en) * 1991-07-30 1993-09-14 Intel Corporation Floating gate nonvolatile memory with reading while writing capability
FR2716743B1 (en) * 1994-02-28 1996-09-27 Sgs Thomson Microelectronics Memory redundancy circuit.
JP3059076B2 (en) * 1995-06-19 2000-07-04 シャープ株式会社 Nonvolatile semiconductor memory device
US6317349B1 (en) * 1999-04-16 2001-11-13 Sandisk Corporation Non-volatile content addressable memory
US6484271B1 (en) * 1999-09-16 2002-11-19 Koninklijke Philips Electronics N.V. Memory redundancy techniques
US6307787B1 (en) * 2000-07-25 2001-10-23 Advanced Micro Devices, Inc. Burst read incorporating output based redundancy

Also Published As

Publication number Publication date
CN1432153A (en) 2003-07-23
TW587255B (en) 2004-05-11
ATE262700T1 (en) 2004-04-15
BR0111245A (en) 2003-06-03
KR100915450B1 (en) 2009-09-04
WO2001093034A2 (en) 2001-12-06
JP2003535430A (en) 2003-11-25
KR20030007812A (en) 2003-01-23
EP1290559B1 (en) 2004-03-24
DE60102466D1 (en) 2004-04-29
US20010048613A1 (en) 2001-12-06
JP4606694B2 (en) 2011-01-05
WO2001093034A3 (en) 2002-05-02
CN1204497C (en) 2005-06-01
EP1290559A2 (en) 2003-03-12
DE60102466T2 (en) 2005-02-24
US6396749B2 (en) 2002-05-28

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